Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9959122 | Single cycle instruction pipeline scheduling | Michael Estlick, Jay Fleischman, Kevin A. Hurd, Kelvin D. Goveas, Brian M. Lay | 2018-05-01 |
| 8219780 | Mitigating context switch cache miss penalty | James Callister, Eric Delano, Rohit Bhatia, Shawn Walker | 2012-07-10 |
| 6807625 | Method and apparatus for efficiently generating, storing, and consuming arithmetic flags between producing and consuming macroinstructions when emulating with microinstructions | Patrick Knebel, Rohit Bhatia, Kevin Safford | 2004-10-19 |
| 6707831 | Mechanism for data forwarding | Eric Fetzer, Rohit Bhatia | 2004-03-16 |
| 6591360 | Local stall/hazard detect in superscalar, pipelined microprocessor | Donald Soltis, Rohit Bhatia | 2003-07-08 |