Issued Patents All Time
Showing 1–25 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12034649 | Routing traffics having primary and secondary destinations in communication networks | Victor Ruybalid | 2024-07-09 |
| 11544174 | Method and apparatus for protecting trace data of a remote debug session | Loren J. McConnell, Tsvika Kurts, Boris Dolgunov, Vamsi Krishna Jakkampudi, Marcus Winston | 2023-01-03 |
| 10846439 | Functional safety over trace-and-debug | Riccardo Locatelli, Peter Lachner, Riccardo Mariani, Michael Paulitsch | 2020-11-24 |
| 10725848 | Supporting hang detection and data recovery in microprocessor systems | Tsvika Kurts, Ki Wook Yoon, Michael J. St. Clair, Larisa Novakovsky, Hisham Shafi +3 more | 2020-07-28 |
| 9641556 | Apparatus and method for identifying constituents in a social network | Timothy Joseph Potter, Jason Westigard, II, John Joseph De Olivera, Erik Lee Huddleston, Bryan Horne +3 more | 2017-05-02 |
| 9483374 | PSMI using at-speed scan capture | Vinothkumar V. Ethiraj | 2016-11-01 |
| 9288123 | Method and system for temporal correlation of social signals | John Joseph De Oliveira, Erik Lee Hudleston, Brian Huddleston | 2016-03-15 |
| 8886979 | Methods and apparatuses for reducing step loads of processors | Rohit Bhatia, Chris Bostak, Richard Blumberg, Blaine Stackhouse, Steve Undy | 2014-11-11 |
| 8479029 | Methods and apparatuses for reducing step loads of processors | Rohit Bhatia, Chris Bostak, Richard Blumberg, Blaine Stackhouse, Steve Undy | 2013-07-02 |
| 7992017 | Methods and apparatuses for reducing step loads of processors | Rohit Bhatia, Chris Bostak, Richard Blumberg, Blaine Stackhouse, Steve Undy | 2011-08-02 |
| 7774658 | Method and apparatus to search for errors in a translation look-aside buffer | Jeremy Petsinger | 2010-08-10 |
| 7725899 | Method and apparatus for communicating information between lock stepped processors | Jeremy Petsinger | 2010-05-25 |
| 7409524 | System and method for responding to TLB misses | Rohit Bhatia, Karl Brummel | 2008-08-05 |
| 7398419 | Method and apparatus for seeding differences in lock-stepped processors | Jeremy Petsinger | 2008-07-08 |
| 7370232 | Method and apparatus for recovery from loss of lock step | — | 2008-05-06 |
| 7343479 | Method and apparatus for implementing two architectures in a chip | Patrick Knebel, Donald Soltis, Joel D. Lamb, Stephen R. Undy, Russell C. Brockmann | 2008-03-11 |
| 7296181 | Lockstep error signaling | Eric Delano | 2007-11-13 |
| 7290169 | Core-level processor lockstepping | Christopher L. Lyles, Eric Delano | 2007-10-30 |
| 7287185 | Architectural support for selective use of high-reliability mode in a computer system | Donald Soltis | 2007-10-23 |
| 7237144 | Off-chip lockstep checking | Donald Soltis, Eric Delano | 2007-06-26 |
| 7155721 | Method and apparatus for communicating information between lock stepped processors | Jeremy Petsinger | 2006-12-26 |
| 7139936 | Method and apparatus for verifying the correctness of a processor behavioral model | Jeremy Petsinger, Karl Brummel, Russell C. Brockmann, Bruce Long, Patrick Knebel | 2006-11-21 |
| 7100097 | Detection of bit errors in maskable content addressable memories | Benjamin J. Patella, Ronny Lee Arnold, Cameron McNairy | 2006-08-29 |
| 7085959 | Method and apparatus for recovery from loss of lock step | — | 2006-08-01 |
| 7003691 | Method and apparatus for seeding differences in lock-stepped processors | Jeremy Petsinger | 2006-02-21 |