Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12332733 | Determining an error handling mode | Michael T. Klinglesmith | 2025-06-17 |
| 9842015 | Instruction and logic for machine checking communication | Ashok Raj, Mohan J. Kumar, Jose A. Vargas, William G. Auld, Theodros Yigzaw +2 more | 2017-12-12 |
| 9495233 | Error framework for a microprocesor and system | David Heckman, Jenna Mayfield, Scott Hoyt | 2016-11-15 |
| 9483293 | Technology abstraction layer | Don Soltis | 2016-11-01 |
| 9063855 | Fault handling at a transaction level by employing a token and a source-to-destination paradigm in a processor-based system | Anil Agrawal, Jenna Mayfield, Eric Andrew Gouldey, Mark Millican | 2015-06-23 |
| 7487398 | Microprocessor design support for computer system and platform validation | Ayman G. Abdo, Piyush Desai, Quinn W. Merrell | 2009-02-03 |
| 7120755 | Transfer of cache lines on-chip between processing cores in a multi-core system | Sujat Jamil, Quinn W. Merrell | 2006-10-10 |
| 7100097 | Detection of bit errors in maskable content addressable memories | Benjamin J. Patella, Ronny Lee Arnold, Kevin Safford | 2006-08-29 |
| 7032134 | Microprocessor design support for computer system and platform validation | Ayman G. Abdo, Piyush Desai, Quinn W. Merrell | 2006-04-18 |