Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
MK

Michael T. Klinglesmith — 47 Patents

Intel: 36 patents #1,000 of 30,777Top 4%
SISifive: 8 patents #6 of 55Top 15%
SSSk Hynix Nand Product Solutions: 2 patents #26 of 148Top 20%
Overall (All Time): #59,703 of 4,157,543Top 2%
47 Patents All Time
Michael T. Klinglesmith has been granted 47 US patents while listed as an inventor at Intel. The first was granted in 2011 and the most recent in December 2025. Michael T. Klinglesmith ranks #59,703 of 4,157,543 US inventors in our database (top 1.4%). Patent records list Michael T. Klinglesmith in Chambéry, OR, FR.

Patents per Year

Patents granted per year, 2011 to 2025Bar chart with a peak of 9 patents in 2025.peak 92011: 1 patents20112012: 1 patents2013: 2 patents20132014: 8 patents2015: 8 patents20152016: 5 patents2017: 3 patents20172018: 5 patents2020: 1 patents20202021: 1 patents2022: 1 patents20222023: 1 patents2024: 1 patents20242025: 9 patents2025

Issued Patents All Time

Showing 1–25 of 47 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12493551 Cache coherency state request vector encoding and use thereof Wesley Waylon Terpstra, Eric Andrew Gouldey, Henry Cook 2025-12-09
12386764 Selective transfer of data including a priority byte Eric Andrew Gouldey, Wesley Waylon Terpstra 2025-08-12
12332799 Speculative request indicator in request message Wesley Waylon Terpstra, Eric Andrew Gouldey, Henry Cook 2025-06-17
12332733 Determining an error handling mode Cameron McNairy 2025-06-17
12306772 Orderability of operations Eric Andrew Gouldey, Henry Cook, Wesley Waylon Terpstra 2025-05-20
12248401 Eviction operations based on eviction message types of different priorities Eric Andrew Gouldey, Wesley Waylon Terpstra 2025-03-11
12204462 Downgrading a permission associated with data stored in a cache Eric Andrew Gouldey, Wesley Waylon Terpstra 2025-01-21
12197335 Canceling prefetch of cache blocks based on an address and a bit field Eric Andrew Gouldey, Wesley Waylon Terpstra 2025-01-14
12189544 Transmitting a response with a request and state information about the request Eric Andrew Gouldey, Wesley Waylon Terpstra 2025-01-07
12079149 Presentation of direct accessed storage under a logical drive model Thomas M. Slaight, Sivakumar Radhakrishnan, Mark A. Schmisseur, Pankaj Kumar, Saptarshi Mondal +9 more 2024-09-03
11604746 Presentation of direct accessed storage under a logical drive model Thomas M. Slaight, Sivakumar Radhakrishnan, Mark A. Schmisseur, Pankaj Kumar, Saptarshi Mondal +9 more 2023-03-14
11476168 Die stack override for die testing Terrence Huat Hin Tan, Rehan Sheikh, Sukhbinder Takhar, Shi Hou Chong, Kok Hin Oon +3 more 2022-10-18 $11,317,000
11144387 Apparatus, systems, and methods to detect and/or correct bit errors using an in band link over a serial peripheral interface Zhenyu Zhu, William A. Stevens, Mikal C. Hunsaker 2021-10-12 $32,982,000
10754808 Bus-device-function address space mapping Prashant Sethi, David J. Harriman, Reuven Rozic, Shanthanand Kutuva Rabindrananth 2020-08-25 $27,661,000
10164880 Sending packets with expanded headers Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Blaise Fanning, Rohit Verma, Robert P. Adler 2018-12-25
10157160 Handling a partition reset in a multi-root system Mikal C. Hunsaker, William Knolla, Hartej Singh 2018-12-18 $25,622,000
10133670 Low overhead hierarchical connectivity of cache coherent agents to a coherent fabric Ramadass Nagarajan, Jose Niell, Derek T. Bachand, Ganesh Kumar 2018-11-20 $25,900,000
9990327 Providing multiple roots in a semiconductor device Chang Yong Kang, Robert DeGruijl, Ioannis T. Schoinas, Darren Abramson, Khee Wooi Lee 2018-06-05 $24,427,000
9971711 Tightly-coupled distributed uncore coherent fabric Ramadass Nagarajan, Joydeep Ray 2018-05-15 $21,346,000
9753875 Systems and an apparatus with a sideband interface interconnecting agents with at least one router Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Blaise Fanning, Mohan Nair, Joseph Murray +3 more 2017-09-05 $9,844,000
9690353 System and method for initiating a reduced power mode for one or more functional blocks of a processor based on various types of mode request Douglas R. Moran, Achmed R. Zahir, William Knolla, Hartej Singh, Vasudev Bibikar +3 more 2017-06-27 $7,334,000
9658978 Providing multiple decode options for a system-on-chip (SoC) fabric Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Blaise Fanning, Eran Tamari, Joseph Murray +1 more 2017-05-23 $7,972,000
9489329 Supporting multiple channels of a single interface Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Blaise Fanning, Eran Tamari, Joseph Murray +1 more 2016-11-08 $9,907,000
9448870 Providing error handling support to legacy devices Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Blaise Fanning, Rohit Verma 2016-09-20 $10,814,000
9417821 Presentation of direct accessed storage under a logical drive model Thomas M. Slaight, Sivakumar Radhakrishnan, Mark A. Schmisseur, Pankaj Kumar, Saptarshi Mondal +9 more 2016-08-16 $10,311,000