Issued Patents All Time
Showing 25 most recent of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12417047 | Heterogeneous ML accelerator cluster with flexible system resource balance | Sheng Li, Norman Paul Jouppi, Martin G. Dixon, Daniel Stodolsky, Quoc V. Le +3 more | 2025-09-16 |
| 11372674 | Method, apparatus and system for handling non-posted memory write transactions in a fabric | Robert P. Adler, Robert De Gruijl, Ramadass Nagarajan, Peter J. Elardo | 2022-06-28 |
| 10846126 | Method, apparatus and system for handling non-posted memory write transactions in a fabric | Robert P. Adler, Robert De Gruijl, Ramadass Nagarajan, Peter J. Elardo | 2020-11-24 |
| 10164880 | Sending packets with expanded headers | Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Rohit Verma, Robert P. Adler | 2018-12-25 |
| 9916876 | Ultra low power architecture to support always on path to memory | Suketu Partiwala, Prashanth Kalluraya, Bruce L. Fleming, Shreekant S. Thakkar, Kenneth D. Shoemaker +2 more | 2018-03-13 |
| 9753875 | Systems and an apparatus with a sideband interface interconnecting agents with at least one router | Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Mohan Nair, Joseph Murray +3 more | 2017-09-05 |
| 9658978 | Providing multiple decode options for a system-on-chip (SoC) fabric | Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Eran Tamari, Joseph Murray +1 more | 2017-05-23 |
| 9489329 | Supporting multiple channels of a single interface | Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Eran Tamari, Joseph Murray +1 more | 2016-11-08 |
| 9448870 | Providing error handling support to legacy devices | Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Rohit Verma | 2016-09-20 |
| 9270576 | Aggregating completion messages in a sideband interface | Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Mohan Nair, Joseph Murray +3 more | 2016-02-23 |
| 9213666 | Providing a sideband message interface for system on a chip (SoC) | Robert P. Adler, Eran Tamari, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning | 2015-12-15 |
| 9122815 | Common idle state, active state and credit management for an interface | Robert P. Adler, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Eran Tamari +2 more | 2015-09-01 |
| 9075929 | Issuing requests to a fabric | Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Eran Tamari, Joseph Murray +2 more | 2015-07-07 |
| 9064051 | Issuing requests to a fabric | Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Eran Tamari, Joseph Murray +2 more | 2015-06-23 |
| 9053251 | Providing a sideband message interface for system on a chip (SoC) | Robert P. Adler, Eran Tamari, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning | 2015-06-09 |
| 8929373 | Sending packets with expanded headers | Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Rohit Verma, Robert P. Adler | 2015-01-06 |
| 8874976 | Providing error handling support to legacy devices | Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Rohit Verma | 2014-10-28 |
| 8805926 | Common idle state, active state and credit management for an interface | Robert P. Adler, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Eran Tamari +2 more | 2014-08-12 |
| 8775700 | Issuing requests to a fabric | Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Eran Tamari, Joseph Murray +2 more | 2014-07-08 |
| 8713234 | Supporting multiple channels of a single interface | Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Eran Tamari, Joseph Murray +1 more | 2014-04-29 |
| 8713240 | Providing multiple decode options for a system-on-chip (SoC) fabric | Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Eran Tamari, Joseph Murray +1 more | 2014-04-29 |
| 8711875 | Aggregating completion messages in a sideband interface | Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Mohan Nair, Joseph Murray +3 more | 2014-04-29 |
| 8370558 | Apparatus and method to merge and align data from distributed memory controllers | Rohit Natarajan, Chen-Chi Kuo | 2013-02-05 |
| 8087024 | Multiple multi-threaded processors having an L1 instruction cache and a shared L2 instruction cache | Wilson Liao, Prashant R. Chandra, Jeen-Yuan Miin, Yim Pun | 2011-12-27 |
| 7707266 | Scalable, high-performance, global interconnect scheme for multi-threaded, multiprocessing system-on-a-chip network processor unit | Mark Rosenbluth, Matthew J. Adiletta, Jeen-Xuan Miin, Bijoy Bose | 2010-04-27 |