Issued Patents All Time
Showing 25 most recent of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12046577 | Stacked memory with interface providing offset interconnects | Pete D. Vogt, Andre Schaefer, Warren R. Morrow, John B. Halbert, Jin-Sung Kim | 2024-07-23 |
| 11909841 | System, apparatus and method for adaptive peer-to-peer communication with edge platform | Francesc Guim Bernat, Kshitij A. Doshi, Vinodh Gopal, Ned M. Smith | 2024-02-20 |
| 11594801 | Mmwave dielectric waveguide interconnect topology for automotive applications | Georgios Dogiamis, Sasha N. Oster, Telesphor Kamgaing, Erich N. Ewy, Adel A. Elsherbini +1 more | 2023-02-28 |
| 11437693 | Mmwave waveguides featuring power-over-waveguide technology for automotive applications | Georgios Dogiamis, Sasha N. Oster, Telesphor Kamgaing, Erich N. Ewy, Adel A. Elsherbini +1 more | 2022-09-06 |
| 10514305 | Induced thermal gradients | — | 2019-12-24 |
| 9916876 | Ultra low power architecture to support always on path to memory | Suketu Partiwala, Prashanth Kalluraya, Bruce L. Fleming, Shreekant S. Thakkar, Sridhar Lakshmanamurthy +2 more | 2018-03-13 |
| 9798369 | Indicating critical battery status in mobile devices | Ivan Herrera Mejia, Ryan D. Wells | 2017-10-24 |
| 9768148 | Stacked memory with interface providing offset interconnects | Pete D. Vogt, Andre Schaefer, Warren R. Morrow, John B. Halbert, Jin-Sung Kim | 2017-09-19 |
| 9658678 | Induced thermal gradients | — | 2017-05-23 |
| 9627357 | Stacked memory allowing variance in device interconnects | Pete D. Vogt | 2017-04-18 |
| 9490003 | Induced thermal gradients | — | 2016-11-08 |
| 9396787 | Memory operations using system thermal sensor data | Paul Fahey | 2016-07-19 |
| 9384351 | Method and apparatus for implementing a secure boot using multiple firmware sources | Ivan Herrera Mejia | 2016-07-05 |
| 9335808 | Indicating critical battery status in mobile devices | Ivan Herrera Mejia, Ryan D. Wells | 2016-05-10 |
| 9104540 | Dynamic memory performance throttling | Brian Toronyi | 2015-08-11 |
| 8971087 | Stacked memory with interface providing offset interconnects | Pete D. Vogt, Andre Schaefer, Warren R. Morrow, John B. Halbert, Jin-Sung Kim | 2015-03-03 |
| 7877619 | Power mode control method and circuitry | Ramana Rachakonda, Blaise Fanning, Anil K. Sabbavarapu, Belliappa Kuttanna, Rajesh Patel +3 more | 2011-01-25 |
| 7685451 | Method and apparatus to limit current-change induced voltage changes in a microcircuit | James S. Burns, Sudarshan Kumar, Tom E. Wang, David J. Ayers, Vivek Tiwari | 2010-03-23 |
| 6898694 | High instruction fetch bandwidth in multithread processor using temporary instruction cache to deliver portion of cache line in subsequent clock cycle | Sailesh Kottapalli, James S. Burns | 2005-05-24 |
| 6088793 | Method and apparatus for branch execution on a multiple-instruction-set-architecture microprocessor | Kin-Yip Liu, Millind Mital | 2000-07-11 |
| 6082421 | Finger jointer | Richard J. Nicol, Brock E. Ferguson | 2000-07-04 |
| 6055652 | Multiple segment register use with different operand size | Nazar Zaidi, Gary N. Hammond | 2000-04-25 |
| 6049897 | Multiple segment register use with different operand size | Nazar Zaidi, Gary N. Hammond | 2000-04-11 |
| 5978900 | Renaming numeric and segment registers using common general register pool | Kin-Yip Liu, Gary N. Hammond, Anand Pai | 1999-11-02 |
| 5802605 | Physical address size selection and page size selection in an address translator | Donald B. Alpert, Kevin C. Kahn, Konrad K. Lai | 1998-09-01 |