Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › High instruction fetch bandwidth in multithread processor using temporary instruction cache to deliver portion of cache line in subsequent clock cycle

High instruction fetch bandwidth in multithread processor using temporary instruction cache to deliver portion of cache line in subsequent clock cycle

US Patent 6898694 · Granted May 24, 2005

Estimated economic value: $30,688,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Methods and system for the reconstruction of drug response and disease networks 2025
Pharmacogenomic decision support for modulators of the NMDA, glycine, and AMPA r2024
Systems and methods for multi-factor location- based device verification2024
Stacked memory with interface providing offset interconnects2024
Methods and system for the reconstruction of drug response and disease networks 2024
System, apparatus and method for adaptive peer-to-peer communication with edge p2024
Systems and methods for multi-factor location-based device verification2024
Mmwave dielectric waveguide interconnect topology for automotive applications2023
Mmwave waveguides featuring power-over-waveguide technology for automotive appli2022
Systems and methods for multi-factor location-based device verification2022
Monitoring the operation of a processor2021
Individual and cohort pharmacological phenotype prediction platform2020