Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
JH

John B. Halbert — 99 Patents

Intel: 95 patents #228 of 30,777Top 1%
TRTahoe Research: 1 patents #81 of 215Top 40%
VTVlsi Technology: 1 patents #349 of 594Top 60%
Beaverton, OR: #28 of 3,140 inventorsTop 1%
Oregon: #221 of 28,073 inventorsTop 1%
Overall (All Time): #14,805 of 4,157,543Top 1%
99 Patents All Time
John B. Halbert has been granted 99 US patents while listed as an inventor at Intel. The first was granted in 1991 and the most recent in July 2024. John B. Halbert ranks #14,805 of 4,157,543 US inventors in our database (top 0.36%). Patent records list John B. Halbert in Beaverton, OR, US.

Issued Patents All Time

Showing 1–25 of 99 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12046577 Stacked memory with interface providing offset interconnects Pete D. Vogt, Andre Schaefer, Warren R. Morrow, Jin-Sung Kim, Kenneth D. Shoemaker 2024-07-23
11010304 Memory with reduced exposure to manufacturing related data corruption errors Uksong Kang, Kjersten E. Criss, Rajat Agarwal 2021-05-18 $44,170,000
10949296 On-die ECC with error counter and internal address generation Kuljit S. Bains 2021-03-16 $38,556,000
10810079 Memory device error check and scrub mode and error transparency Kuljit S. Bains 2020-10-20 $43,271,000
10572343 Targeted aliasing single error correction (SEC) code Kjersten E. Criss 2020-02-25 $18,813,000
10522207 Performance of additional refresh operations during self-refresh mode Kuljit S. Bains, Shay Fux 2019-12-31 $25,528,000
10496473 Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC) Debaleena Das, Bill Nale, Kuljit S. Bains 2019-12-03 $19,496,000
10489083 Flexible command addressing for memory Kuljit S. Bains 2019-11-26 $25,149,000
10459809 Stacked memory chip device with enhanced data protection capability Hussein Alameer, Uksong Kang, Kjersten E. Criss, Rajat Agarwal, Wei Wu 2019-10-29 $25,165,000
10242727 Reduction of power consumption in memory devices during refresh modes Christopher E. Cox, Kuljit S. Bains 2019-03-26 $18,583,000
10210925 Row hammer refresh command Kuljit S. Bains, Christopher P. Mozak, Theodore Z. Schoenborn, Zvika Greenfield 2019-02-19 $27,334,000
10127101 Memory device error check and scrub mode and error transparency Kuljit S. Bains 2018-11-13 $26,640,000
10121532 Apparatus, method and system for performing successive writes to a bank of a dynamic random access memory Kuljit S. Bains 2018-11-06 $18,970,000
10109340 Precharging and refreshing banks in memory device with bank group architecture Kuljit S. Bains, Nadav Bonen, Tomer Levy 2018-10-23 $21,867,000
10108512 Validation of memory on-die error correction code Kuljit S. Bains 2018-10-23 $21,867,000
10083737 Row hammer monitoring based on stored row hammer threshold value Kuljit S. Bains 2018-09-25 $26,257,000
9984737 Reduction of power consumption in memory devices during refresh modes Christopher E. Cox, Kuljit S. Bains 2018-05-29 $28,242,000
9953694 Memory controller-controlled refresh abort Bruce Querbach, Kuljit S. Bains 2018-04-24 $19,097,000
9904591 Device, system and method to restrict access to data error information Kuljit S. Bains, Debaleena Das, Bill Nale 2018-02-27 $23,267,000
9865326 Row hammer refresh command Kuljit S. Bains, Christopher P. Mozak, Theodore Z. Schoenborn, Zvika Greenfield 2018-01-09 $14,051,000
9842021 Memory device check bit read mode Kuljit S. Bains 2017-12-12 $18,742,000
9824743 Memory refresh operation with page open Bruce Querbach, Kuljit S. Bains 2017-11-21 $11,290,000
9817714 Memory device on-die error checking and correcting code Kuljit S. Bains, Kjersten E. Criss 2017-11-14 $11,178,000
9811420 Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC) Debaleena Das, Bill Nale, Kuljit S. Bains 2017-11-07 $13,901,000
9768148 Stacked memory with interface providing offset interconnects Pete D. Vogt, Andre Schaefer, Warren R. Morrow, Jin-Sung Kim, Kenneth D. Shoemaker 2017-09-19 $8,005,000