| 12417195 |
Techniques for command bus training to a memory device |
Steven T. TAYLOR, Alvin Shing Chye Goh |
2025-09-16 |
|
| 12355445 |
Techniques for duty cycle correction |
Ralph S. Li, Chin Wah Lim, Mahmoud Elassal, Anant Balakrishnan, Isaac Ali |
2025-07-08 |
|
| 12321214 |
Fast self-refresh exit power state |
Robert J. Royer, Jr., Aaron Martin, Alex Thomas, Tomer Levy, Noam Lupovich |
2025-06-03 |
|
| 12230569 |
Apparatus and method to increase effective capacitance with layout staples |
Kushal Sreedhar, Mahmoud Elassal |
2025-02-18 |
|
| 12093195 |
Techniques for command bus training to a memory device |
Steven T. TAYLOR, Alvin Shing Chye Goh |
2024-09-17 |
$19,251,000 |
| 11916554 |
Techniques for duty cycle correction |
Ralph S. Li, Chin Wah Lim, Mahmoud Elassal, Anant Balakrishnan, Isaac Ali |
2024-02-27 |
$28,450,000 |
| 11675532 |
Memory command that specifies one of multiple possible write data values where the write data is not transported over a memory data bus |
Christopher E. Cox |
2023-06-13 |
$864,000 |
| 11675716 |
Techniques for command bus training to a memory device |
Steven T. TAYLOR, Alvin Shing Chye Goh |
2023-06-13 |
$22,204,000 |
| 11335395 |
Applying chip select for memory device identification and power management control |
Christopher E. Cox, Kuljit S. Bains, James A. McCall, Akshith Vasanth, Bill Nale |
2022-05-17 |
$14,251,000 |
| 11226762 |
Memory command that specifies one of multiple possible write data values where the write data is not transported over a memory data bus |
Christopher E. Cox |
2022-01-18 |
$1,238,000 |
| 11159154 |
Power gate ramp-up control apparatus and method |
Eliyah Kilada |
2021-10-26 |
$21,268,000 |
| 11074959 |
DDR memory bus with a reduced data strobe signal preamble timespan |
James A. McCall, Christopher E. Cox, Yan Fu, Robert J. Friar, Hsien-Pao Yang |
2021-07-27 |
$27,337,000 |
| 11061590 |
Efficiently training memory device chip select control |
Tonia G. Morris, Christopher E. Cox |
2021-07-13 |
$34,958,000 |
| 11037607 |
Strong arm latch with wide common mode range |
Raymond Chong, Bee Min Teng |
2021-06-15 |
$33,380,000 |
| 10923164 |
Dual power I/O transmitter |
Hariprasath Venkatram, Mohammed G. Mostofa, Rajesh INTI, Roger K. Cheng, Aaron Martin +5 more |
2021-02-16 |
$35,223,000 |
| 10839887 |
Applying chip select for memory device identification and power management control |
Christopher E. Cox, Kuljit S. Bains, James A. McCall, Akshith Vasanth, Bill Nale |
2020-11-17 |
$36,756,000 |
| 10802996 |
Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines |
James A. McCall, Bryan K. Casper |
2020-10-13 |
$29,561,000 |
| 10672438 |
Dynamic reconfigurable dual power I/O receiver |
Mohammed G. Mostofa, Roger K. Cheng, Aaron Martin, Pavan Kumar Kappagantula, Hsien-Pao Yang |
2020-06-02 |
$32,838,000 |
| 10573272 |
Device, method and system for providing a delayed clock signal to a circuit for latching data |
Senthil Kumar Sampath |
2020-02-25 |
$18,813,000 |
| 10541018 |
DDR memory bus with a reduced data strobe signal preamble timespan |
James A. McCall, Christopher E. Cox, Yan Fu, Robert J. Friar, Hsien-Pao Yang |
2020-01-21 |
$31,546,000 |
| 10516439 |
Interference testing |
Alexey Kostinsky, Tomer Levy, Paul S. Cheses, Danny Naiger, Theodore Z. Schoenborn +2 more |
2019-12-24 |
$26,956,000 |
| 10446222 |
Memory subsystem I/O performance based on in-system empirical testing |
Theodore Z. Schoenborn |
2019-10-15 |
$18,012,000 |
| 10437746 |
Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines |
James A. McCall, Bryan K. Casper |
2019-10-08 |
$19,521,000 |
| 10416912 |
Efficiently training memory device chip select control |
Tonia G. Morris, Christopher E. Cox |
2019-09-17 |
$19,673,000 |
| 10373948 |
On-die system electrostatic discharge protection |
Victor Zia, Gabriel J. Thompson |
2019-08-06 |
$15,127,000 |
