Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10496152 | Power control techniques for integrated PCIe controllers | Lily P. Looi, Shaun M. Conrad | 2019-12-03 |
| 10347319 | Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system | Christopher P. Mozak, Kevin B. Moore, John V. Lovelace, Theodore Z. Schoenborn, Christopher E. Yunker | 2019-07-09 |
| 10282341 | Method, apparatus and system for configuring a protocol stack of an integrated circuit chip | Marcus W. Song, Deepak Rangaraj, Avinash N. Ananthakrishnan, Robert J. Hayes, Aimee D. Wood +2 more | 2019-05-07 |
| 9910814 | Method, apparatus and system for single-ended communication of transaction layer packets | Su Wei Lim, Mikal C. Hunsaker, Rohit Verma, Lily P. Looi, Ronald W. Swartz +2 more | 2018-03-06 |
| 9734116 | Method, apparatus and system for configuring a protocol stack of an integrated circuit chip | Marcus W. Song, Deepak Rangaraj, Avinash N. Ananthakrishnan, Robert J. Hayes, Aimee D. Wood +2 more | 2017-08-15 |
| 9373365 | Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system | Christopher P. Mozak, Kevin B. Moore, John V. Lovelace, Theodore Z. Schoenborn, Christopher E. Yunker | 2016-06-21 |
| 9330734 | Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system | Christopher P. Mozak, Kevin B. Moore, John V. Lovelace, Theodore Z. Schoenborn, Christopher E. Yunker | 2016-05-03 |
| 8868992 | Robust memory link testing using memory controller | Theodore Z. Schoenborn, Philip Abraham, Christopher P. Mozak, David G. Ellis, Jay Nejedlo +6 more | 2014-10-21 |
| 8819474 | Active training of memory command timing | Theodore Z. Schoenborn, John V. Lovelace, Christopher P. Mozak | 2014-08-26 |
| 8582374 | Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system | Christopher P. Mozak, Kevin B. Moore, John V. Lovelace, Zale Schoenborn, Chris Yunker | 2013-11-12 |
| 8331176 | Method and system for evaluating effects of signal phase difference on a memory system | Christopher P. Mozak, Kevin B. Moore, John V. Lovelace, Zale Schoenborn, Christopher E. Yunker | 2012-12-11 |
| 7886174 | Memory link training | Christopher P. Mozak, Stanley S. Kulick | 2011-02-08 |
| 7779188 | System and method to reduce memory latency in microprocessor systems connected with a bus | Harris Joyce, Balaji Ramamoorthy, Jeffrey D. Gilbert | 2010-08-17 |
| 7590805 | Monitor implementation in a multicore processor with inclusive LLC | Krishnakanth V. Sistla | 2009-09-15 |