Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10083735 | Apparatuses, methods, and systems for package on package memory refresh and self-refresh rate management | Xiuting C. Man | 2018-09-25 |
| 10025732 | Preserving deterministic early valid across a clock domain crossing | Bezan KAPADIA, James M. Shehadi, Amir Ali Radjai | 2018-07-17 |
| 9653144 | Apparatuses, methods, and systems for package on package memory refresh and self-refresh rate management | Xiuting C. Man | 2017-05-16 |
| 9442864 | Bridging circuitry between a memory controller and request agents in a system having multiple system memory protection schemes | Uday Savagaonkar, Siddhartha Chhabra, Men Long, Alpa T. Narendra Trivedi, Carlos Ornelas +2 more | 2016-09-13 |
| 9336156 | Method and apparatus for cache line state update in sectored cache with line state tracker | Zhongying Zhang, Erik G. Hallnor, Jeffrey L. Miller | 2016-05-10 |
| 9285826 | Deterministic clock crossing | Erin Francom, Jason Anthony Bessette | 2016-03-15 |
| 9274544 | Sideband initialization | — | 2016-03-01 |
| 9143120 | Mechanisms for clock gating | Randy B. Osborne, Erin Francom, Thomas P. Thomas | 2015-09-22 |
| 8977811 | Scalable schedulers for memory controllers | Philip Abraham, Randy B. Osborne | 2015-03-10 |
| 8902956 | On-package input/output clustered interface having full and half-duplex modes | Thomas P. Thomas, Randy B. Osborne | 2014-12-02 |
| 8463987 | Scalable schedulers for memory controllers | Philip Abraham, Randy B. Osborne | 2013-06-11 |
| 8327222 | Mechanism for adjacent-symbol error correction and detection | James W. Alexander, Thomas J. Holman, Mark A. Heap | 2012-12-04 |
| 7886174 | Memory link training | Bryan L. Spry, Christopher P. Mozak | 2011-02-08 |
| 7509560 | Mechanism for adjacent-symbol error correction and detection | James W. Alexander, Thomas J. Holman, Mark A. Heap | 2009-03-24 |
| 7386643 | Mechanism to guarantee forward progress for incoming coherent input/output (I/O) transactions for caching I/O agent on address conflict with processor transactions | Sin S. Tan, Rajesh S. Pamujula | 2008-06-10 |
| 7103746 | Method of sparing memory devices containing pinned memory | — | 2006-09-05 |
| 7047374 | Memory read/write reordering | Suneeta Sah, Varin Udompanyanan, Chitra Natarajan, Hrishikesh S. Pai | 2006-05-16 |
| 6832268 | Mechanism to guarantee forward progress for incoming coherent input/output (I/O) transactions for caching I/O agent on address conflict with processor transactions | Sin S. Tan, Rajesh S. Pamujula | 2004-12-14 |
| 6813665 | Interrupt method, system and medium | Linda J. Rankin, Michael Cekleov | 2004-11-02 |