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Scalably mechanism to implement an instruction that monitors for writes to an address |
Yen-Cheng Liu, Bahaa Fahim, Jeffrey D. Chamberlain, Stephen R. Van Doren, Antonio Juan |
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Supporting hierarchical ordering points in a microprocessor system |
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Shared flow control credits |
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2018-04-24 |
| 9785223 |
Power management in an uncore fabric |
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2017-10-10 |
| 9710041 |
Masking a power state of a core of a processor |
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2017-07-18 |
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Method and apparatus for cache line state update in sectored cache with line state tracker |
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2016-05-10 |
| 8392657 |
Monitoring cache usage in a distributed shared cache |
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2013-03-05 |
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Domain-based cache management, including domain event based priority demotion |
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2012-11-20 |
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Power state transition initiation control of memory interconnect based on early warning signal, memory response time, and wakeup delay |
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2012-01-03 |