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Apparatus and method to identify the source of an interrupt |
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Apparatus and method to identify the source of an interrupt |
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Core-only system management interrupt |
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Systems and methods for enhancing BIOS performance by alleviating code-size limitations |
Leon Polishuk, Pavel Konev, Julius Mandelblat |
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Pipelined prefetcher for parallel advancement of multiple data streams |
Leeor Peled, Joseph Nuzman |
2018-12-18 |
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Apparatus and method for memory-hierarchy aware producer-consumer instruction |
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2018-06-05 |
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Cache memory staged reopen |
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2017-11-28 |
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Masking a power state of a core of a processor |
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Joseph Nuzman, Alexander Gendler |
2017-06-20 |
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Shani Rehana, Alexander Gendler |
2017-01-03 |
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Restricting clock signal delivery in a processor |
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Method and apparatus for cache line write back operation |
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Adaptive hierarchical cache policy in a microprocessor |
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Cache circuit having a tag array with smaller latency than a data array |
— |
2016-06-14 |
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Reduced power mode of a cache unit |
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2016-06-07 |
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Multi latency configurable cache |
Alexander Gendler, Ohad Stauber |
2015-03-31 |
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Method and apparatus for error correction in a cache |
Stanislav Shwartsman, Raanan Sade, Arijit Biswas |
2015-03-24 |
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Posting weakly ordered transactions |
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Device, system and method of managing a resource request |
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2011-06-07 |