Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11900115 | Apparatus and method to identify the source of an interrupt | Ashok Raj, Andreas Kleen, Gilbert Neiger, Beeman C. Strong, Jason W. Brandt +4 more | 2024-02-13 |
| 11614939 | Apparatus and method to identify the source of an interrupt | Ashok Raj, Andreas Kleen, Gilbert Neiger, Beeman C. Strong, Jason W. Brandt +4 more | 2023-03-28 |
| 11048512 | Apparatus and method to identify the source of an interrupt | Ashok Raj, Andreas Kleen, Gilbert Neiger, Beeman C. Strong, Jason W. Brandt +4 more | 2021-06-29 |
| 10990534 | Device, system and method to facilitate disaster recovery for a multi-processor platform | Wei-Chih Chen, Eswaramoorthi Nallusamy, Mark A. Schmisseur, Eric Rasmussen, Stephen R. Van Doren +1 more | 2021-04-27 |
| 10775434 | System, apparatus and method for probeless field scan of a processor | Michael Mishaeli, Edward Brazil, Alexander Gendler | 2020-09-15 |
| 10725848 | Supporting hang detection and data recovery in microprocessor systems | Tsvika Kurts, Ki Wook Yoon, Michael J. St. Clair, Hisham Shafi, William Penner +3 more | 2020-07-28 |
| 10719326 | Communicating via a mailbox interface of a processor | Alexander Gendler, Ariel Szapiro | 2020-07-21 |
| 10628542 | Core-only system management interrupt | Tsvika Kurts, Alexander Gendler, Anwar Azaarura Zaa'Rura, Afik Sela, Genadi Kazakevich +2 more | 2020-04-21 |
| 10175992 | Systems and methods for enhancing BIOS performance by alleviating code-size limitations | Leon Polishuk, Pavel Konev, Julius Mandelblat | 2019-01-08 |
| 10157136 | Pipelined prefetcher for parallel advancement of multiple data streams | Leeor Peled, Joseph Nuzman | 2018-12-18 |
| 9990287 | Apparatus and method for memory-hierarchy aware producer-consumer instruction | Shlomo Raikin, Raanan Sade, Robert Valentine, Julius Mandelblat, Ron Shalev | 2018-06-05 |
| 9830272 | Cache memory staged reopen | Iris Sorani, Joseph Nuzman | 2017-11-28 |
| 9710041 | Masking a power state of a core of a processor | Alexander Gendler, Krishnakanth V. Sistla, Vivek Garg, Dean Mulla, Ashish V. Choubal +2 more | 2017-07-18 |
| 9684595 | Adaptive hierarchical cache policy in a microprocessor | Joseph Nuzman, Alexander Gendler | 2017-06-20 |
| 9535476 | Apparatus and method to transfer data packets between domains of a processor | Shani Rehana, Alexander Gendler | 2017-01-03 |
| 9471088 | Restricting clock signal delivery in a processor | Alexander Gendler, Efraim Rotem, Julius Mandelblat, Alexander Lyakhov, George Leifman +3 more | 2016-10-18 |
| 9471494 | Method and apparatus for cache line write back operation | Rajesh M. Sankaran, Neil Schaper, Joseph Nuzman, Yen-Cheng Liu, Gilbert Neiger +1 more | 2016-10-18 |
| 9448879 | Apparatus and method for implement a multi-level memory hierarchy | Theodros Yigzaw, Oded Lempel, Hisham Shafi, Geeyarpuram N. Santhanakrishnan, Jose A. Vargas +6 more | 2016-09-20 |
| 9378148 | Adaptive hierarchical cache policy in a microprocessor | Joseph Nuzman, Alexander Gendler | 2016-06-28 |
| 9367464 | Cache circuit having a tag array with smaller latency than a data array | — | 2016-06-14 |
| 9360924 | Reduced power mode of a cache unit | Alexander Gendler, Ariel Sabba, Niv Tokman | 2016-06-07 |
| 8996833 | Multi latency configurable cache | Alexander Gendler, Ohad Stauber | 2015-03-31 |
| 8990512 | Method and apparatus for error correction in a cache | Stanislav Shwartsman, Raanan Sade, Arijit Biswas | 2015-03-24 |
| 8347035 | Posting weakly ordered transactions | Geeyarpuram N. Santhanakrishnan, Julius Mandelblat, Ehud Cohen, Zeev Offen, Michelle J. Moravan +2 more | 2013-01-01 |
| 7958510 | Device, system and method of managing a resource request | Abraham Mendelson, Julius Mandelblat | 2011-06-07 |