| 12333305 |
Delayed cache writeback instructions for improved data sharing in manycore processors |
Wim Heirman, Ibrahim Hur |
2025-06-17 |
| 12050915 |
Instruction and logic for code prefetching |
Wim Heirman, Ibrahim Hur |
2024-07-30 |
| 11526483 |
Storage architectures for graph analysis applications |
Jason Howard, Ibrahim Hur, Ivan B. Ganev, Fabrizio Petrini, Joshua B. Fryman |
2022-12-13 |
| 11256626 |
Apparatus, method, and system for enhanced data prefetching based on non-uniform memory access (NUMA) characteristics |
Wim Heirman, Ibrahim Hur, Ugonna Echeruo, Kristof Du Bois |
2022-02-22 |
| 11010182 |
Instruction window centric processor simulation |
Lieven Eeckhout, Wim Heirman, Trevor E. Carlson |
2021-05-18 |
| 10942851 |
System, apparatus and method for dynamic automatic sub-cacheline granularity memory access control |
Wim Heirman, Kristof Du Bois, Ibrahim Hur, Joshua B. Fryman |
2021-03-09 |
| 10877886 |
Storing cache lines in dedicated cache of an idle core |
Wim Heirman, Kristof Du Bois, Yves Vandriessche, Ibrahim Hur, Erik G. Hallnor |
2020-12-29 |
| 10684858 |
Indirect memory fetcher |
Wim Heirman, Kristof Du Bois, Ibrahim Hur, Joshua B. Fryman |
2020-06-16 |
| 10621099 |
Apparatus, method, and system for enhanced data prefetching based on non-uniform memory access (NUMA) characteristics |
Wim Heirman, Ibrahim Hur, Ugonna Echeruo, Kristof Du Bois |
2020-04-14 |
| 10303609 |
Independent tuning of multiple hardware prefetchers |
Wim Heirman, Kristof Du Bois, Yves Vandriessche, Ibrahim Hur |
2019-05-28 |
| 8812808 |
Counter architecture for online DVFS profitability estimation |
Lieven Eeckhout |
2014-08-19 |