Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12204901 | Cache support for indirect loads and indirect stores in graph applications | Robert Pawlowski, Sriram Aananthakrishnan, Joshua B. Fryman | 2025-01-21 |
| 12158852 | Circuitry and methods for direct memory access instruction set architecture support for flexible dense compute using a reconfigurable spatial array | Robert Pawlowski, Bharadwaj Krishnamurthy, Shruti Sharma, Byoungchan Oh, Jing Fang +2 more | 2024-12-03 |
| 11960922 | System, apparatus and method for user space object coherency in a processor | Joshua B. Fryman, Ibrahim Hur, Robert Pawlowski | 2024-04-16 |
| 11630691 | Memory system architecture for multi-threaded processors | Robert Pawlowski, Ankit More, Joshua B. Fryman, Tina C. Zhong, Shaden Smith +5 more | 2023-04-18 |
| 11526483 | Storage architectures for graph analysis applications | Stijn Eyerman, Ibrahim Hur, Ivan B. Ganev, Fabrizio Petrini, Joshua B. Fryman | 2022-12-13 |
| 11360809 | Multithreaded processor core with hardware-assisted task scheduling | William P. Griffin, Jr., Joshua B. Fryman, Sang Phill Park, Robert Pawlowski, Michael D. Abbott +6 more | 2022-06-14 |
| 11106494 | Memory system architecture for multi-threaded processors | Robert Pawlowski, Ankit More, Joshua B. Fryman, Tina C. Zhong, Shaden Smith +5 more | 2021-08-31 |
| 11061742 | System, apparatus and method for barrier synchronization in a multi-threaded processor | Robert Pawlowski, Ankit More, Shaden Smith, Sowmya Pitchaimoorthy, Samkit Jain +3 more | 2021-07-13 |
| 10983793 | Array broadcast and reduction systems and methods | Joshua B. Fryman, Ankit More, Robert Pawlowski, Yigit Demir, Nick Pepperling +3 more | 2021-04-20 |
| 10929132 | Systems and methods for ISA support for indirect loads and stores for efficiently accessing compressed lists in graph applications | Robert Pawlowski, Scott Hagan Schmittel, Joshua B. Fryman, Wim Heirman, Ankit More +2 more | 2021-02-23 |
| 10795819 | Multi-processor system with configurable cache sub-domains and cross-die memory coherency | Robert Pawlowski, Bharadwaj Krishnamurthy, Vincent Cave, Ankit More, Joshua B. Fryman | 2020-10-06 |
| 10476492 | Structures and operations of integrated circuits having network of configurable switches | Ankit More, Robert Pawlowski, Fabrizio Petrini, Shaden Smith | 2019-11-12 |
| 10296338 | System, apparatus and method for low overhead control transfer to alternate address space in a processor | Brent R. Boswell, Banu Meenakshi Nagasundaram, Michael D. Abbott, Srikanth Dakshinamoorthy, Joshua B. Fryman | 2019-05-21 |
| 6988119 | Fast single precision floating point accumulator using base 32 system | Yatin Hoskote, Sriram R Vangai | 2006-01-17 |