Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12388712 | In-network multicast operations | Robert Pawlowski, Vincent Cave, Shruti Sharma, Fabrizio Petrini, Joshua B. Fryman | 2025-08-12 |
| 12153932 | Techniques for acceleration of a prefix-scan operation | Fabrizio Petrini, Robert Pawlowski, Shruti Sharma, Sowmya Pitchaimoorthy | 2024-11-26 |
| 11989414 | Method and apparatus for compressing and decompressing sparse data sets | Mattheus Cornelis Antonius Adrianus Heddes, Nishit Shah, Torsten Hoefler | 2024-05-21 |
| 11942970 | Compression circuits and methods using tree based encoding of bit masks | Nishit Shah, Mattheus Cornelis Antonius Adrianus Heddes | 2024-03-26 |
| 11848689 | Method and apparatus for compression multiplexing for sparse computations | Mattheus Cornelis Antonius Adrianus Heddes, Nishit Shah | 2023-12-19 |
| 11720252 | Method and apparatus for compressing and decompressing sparse data sets | Mattheus Cornelis Antonius Adrianus Heddes, Nishit Shah, Torsten Hoefler | 2023-08-08 |
| 11630691 | Memory system architecture for multi-threaded processors | Robert Pawlowski, Jason Howard, Joshua B. Fryman, Tina C. Zhong, Shaden Smith +5 more | 2023-04-18 |
| 11360809 | Multithreaded processor core with hardware-assisted task scheduling | William P. Griffin, Jr., Joshua B. Fryman, Jason Howard, Sang Phill Park, Robert Pawlowski +6 more | 2022-06-14 |
| 11106494 | Memory system architecture for multi-threaded processors | Robert Pawlowski, Jason Howard, Joshua B. Fryman, Tina C. Zhong, Shaden Smith +5 more | 2021-08-31 |
| 11061742 | System, apparatus and method for barrier synchronization in a multi-threaded processor | Robert Pawlowski, Shaden Smith, Sowmya Pitchaimoorthy, Samkit Jain, Vincent Cave +3 more | 2021-07-13 |
| 11003619 | Systolic array accelerator systems and methods | Srinivasan Narayanamoorthy, Jayaram Bobba | 2021-05-11 |
| 10983793 | Array broadcast and reduction systems and methods | Joshua B. Fryman, Jason Howard, Robert Pawlowski, Yigit Demir, Nick Pepperling +3 more | 2021-04-20 |
| 10929132 | Systems and methods for ISA support for indirect loads and stores for efficiently accessing compressed lists in graph applications | Robert Pawlowski, Scott Hagan Schmittel, Joshua B. Fryman, Wim Heirman, Jason Howard +2 more | 2021-02-23 |
| 10795819 | Multi-processor system with configurable cache sub-domains and cross-die memory coherency | Robert Pawlowski, Bharadwaj Krishnamurthy, Vincent Cave, Jason Howard, Joshua B. Fryman | 2020-10-06 |
| 10476492 | Structures and operations of integrated circuits having network of configurable switches | Jason Howard, Robert Pawlowski, Fabrizio Petrini, Shaden Smith | 2019-11-12 |
| 10452717 | Technologies for node-degree based clustering of data sets | Ahmet Can Sitik | 2019-10-22 |
| 9998401 | Architecture for on-die interconnect | Surhud Khare, Dinesh Somasekhar, David S. Dunning | 2018-06-12 |
| 9992135 | Apparatus and method for fusion of compute and switching functions of exascale system into a single component by using configurable network-on-chip fabric with distributed dual mode input-output ports and programmable network interfaces | Surhud Khare, Dinesh Somasekhar, David S. Dunning, Nitin Y. Borkar, Shekhar Y. Borkar | 2018-06-05 |
| 9287208 | Architecture for on-die interconnect | Surhud Khare, Dinesh Somasekhar, David S. Dunning | 2016-03-15 |