Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12388712 | In-network multicast operations | Vincent Cave, Shruti Sharma, Fabrizio Petrini, Joshua B. Fryman, Ankit More | 2025-08-12 |
| 12360824 | Return value storage for atomic functions | Fabio Checconi, Fabrizio Petrini | 2025-07-15 |
| 12204901 | Cache support for indirect loads and indirect stores in graph applications | Sriram Aananthakrishnan, Jason Howard, Joshua B. Fryman | 2025-01-21 |
| 12158852 | Circuitry and methods for direct memory access instruction set architecture support for flexible dense compute using a reconfigurable spatial array | Bharadwaj Krishnamurthy, Shruti Sharma, Byoungchan Oh, Jing Fang, Daniel Klowden +2 more | 2024-12-03 |
| 12153932 | Techniques for acceleration of a prefix-scan operation | Ankit More, Fabrizio Petrini, Shruti Sharma, Sowmya Pitchaimoorthy | 2024-11-26 |
| 11960922 | System, apparatus and method for user space object coherency in a processor | Joshua B. Fryman, Jason Howard, Ibrahim Hur | 2024-04-16 |
| 11630691 | Memory system architecture for multi-threaded processors | Ankit More, Jason Howard, Joshua B. Fryman, Tina C. Zhong, Shaden Smith +5 more | 2023-04-18 |
| 11360809 | Multithreaded processor core with hardware-assisted task scheduling | William P. Griffin, Jr., Joshua B. Fryman, Jason Howard, Sang Phill Park, Michael D. Abbott +6 more | 2022-06-14 |
| 11106494 | Memory system architecture for multi-threaded processors | Ankit More, Jason Howard, Joshua B. Fryman, Tina C. Zhong, Shaden Smith +5 more | 2021-08-31 |
| 11061742 | System, apparatus and method for barrier synchronization in a multi-threaded processor | Ankit More, Shaden Smith, Sowmya Pitchaimoorthy, Samkit Jain, Vincent Cave +3 more | 2021-07-13 |
| 10983793 | Array broadcast and reduction systems and methods | Joshua B. Fryman, Ankit More, Jason Howard, Yigit Demir, Nick Pepperling +3 more | 2021-04-20 |
| 10929132 | Systems and methods for ISA support for indirect loads and stores for efficiently accessing compressed lists in graph applications | Scott Hagan Schmittel, Joshua B. Fryman, Wim Heirman, Jason Howard, Ankit More +2 more | 2021-02-23 |
| 10795819 | Multi-processor system with configurable cache sub-domains and cross-die memory coherency | Bharadwaj Krishnamurthy, Vincent Cave, Jason Howard, Ankit More, Joshua B. Fryman | 2020-10-06 |
| 10476492 | Structures and operations of integrated circuits having network of configurable switches | Ankit More, Jason Howard, Fabrizio Petrini, Shaden Smith | 2019-11-12 |