Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11989414 | Method and apparatus for compressing and decompressing sparse data sets | Ankit More, Nishit Shah, Torsten Hoefler | 2024-05-21 |
| 11942970 | Compression circuits and methods using tree based encoding of bit masks | Nishit Shah, Ankit More | 2024-03-26 |
| 11886938 | Message communication between integrated computing devices | Deepak Goel, Torsten Hoefler, Xiaoling Xu | 2024-01-30 |
| 11848689 | Method and apparatus for compression multiplexing for sparse computations | Ankit More, Nishit Shah | 2023-12-19 |
| 11720252 | Method and apparatus for compressing and decompressing sparse data sets | Ankit More, Nishit Shah, Torsten Hoefler | 2023-08-08 |
| 11580388 | Distributed processing architecture | Torsten Hoefler, Deepak Goel, Jonathan R. Belk | 2023-02-14 |
| 11076210 | Distributed processing architecture | Torsten Hoefler, Jonathan R. Belk | 2021-07-27 |
| 10936943 | Providing flexible matrix processors for performing neural network convolution in matrix-processor-based devices | Colin Beaton Verrilli, Natarajan Vaidhyanathan, Koustav Bhattacharya, Robert S. Dreyer | 2021-03-02 |
| 10838862 | Memory controllers employing memory capacity compression, and related processor-based systems and methods | Natarajan Vaidhyanathan, Colin Beaton Verrilli | 2020-11-17 |
| 10747501 | Providing efficient floating-point operations using matrix processors in processor-based systems | Natarajan Vaidhyanathan, Robert S. Dreyer, Colin Beaton Verrilli, Koustav Bhattacharya | 2020-08-18 |
| 10725740 | Providing efficient multiplication of sparse matrices in matrix-processor-based devices | Robert S. Dreyer, Colin Beaton Verrilli, Natarajan Vaidhyanathan, Koustav Bhattacharya | 2020-07-28 |
| 10503661 | Providing memory bandwidth compression using compressed memory controllers (CMCs) in a central processing unit (CPU)-based system | Natarajan Vaidhyanathan, Colin Beaton Verrilli | 2019-12-10 |
| 10467092 | Providing space-efficient storage for dynamic random access memory (DRAM) cache tags | Natarajan Vaidhyanathan, Colin Beaton Verrilli | 2019-11-05 |
| 10236917 | Providing memory bandwidth compression in chipkill-correct memory architectures | Natarajan Vaidhyanathan, Luther James Blackwood, Michael R. Trombley, Colin Beaton Verrilli | 2019-03-19 |
| 10191850 | Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system | Colin Beaton Verrilli, Mark Anthony Rinaldi, Natarajan Vaidhyanathan | 2019-01-29 |
| 10176096 | Providing scalable dynamic random access memory (DRAM) cache management using DRAM cache indicator caches | Natarajan Vaidhyanathan, Colin Beaton Verrilli | 2019-01-08 |
| 10176090 | Providing memory bandwidth compression using adaptive compression in central processing unit (CPU)-based systems | Colin Beaton Verrilli, Natarajan Vaidhyanathan | 2019-01-08 |
| 10152261 | Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based system | Colin Beaton Verrilli, Natarajan Vaidhyanathan | 2018-12-11 |
| 10146693 | Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system | Colin Beaton Verrilli, Mark Anthony Rinaldi, Natarajan Vaidhyanathan | 2018-12-04 |
| 10067706 | Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based system | Colin Beaton Verrilli, Natarajan Vaidhyanathan | 2018-09-04 |
| 10055158 | Providing flexible management of heterogeneous memory systems using spatial quality of service (QoS) tagging in processor-based systems | Colin Beaton Verrilli, Carl A. Waldspurger, Natarajan Vaidhyanathan, Koustav Bhattacharya | 2018-08-21 |
| 9740621 | Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods | Natarajan Vaidhyanathan, Colin Beaton Verrilli | 2017-08-22 |
| 5450351 | Content addressable memory implementation with random access memory | — | 1995-09-12 |