Issued Patents All Time
Showing 1–25 of 98 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12380058 | Hardware-based image/video processing in machine learning-accelerator system-on-chip | Sandeep Pande, Satish Singh, Colin Beaton Verrilli, Vinay MURTHY | 2025-08-05 |
| 12165237 | Memory storage format for supporting machine learning acceleration | Colin Beaton Verrilli, Matthew Simpson, Geoffrey Carlton BERRY, Sandeep Pande | 2024-12-10 |
| 12155402 | Inline decompression | Colin Beaton Verrilli | 2024-11-26 |
| 11362672 | Inline decompression | Colin Beaton Verrilli | 2022-06-14 |
| 11144368 | Providing self-resetting multi-producer multi-consumer semaphores in distributed processor-based systems | Colin Beaton Verrilli | 2021-10-12 |
| 11010313 | Method, apparatus, and system for an architecture for machine learning acceleration | Colin Beaton Verrilli, Rexford Hill | 2021-05-18 |
| 10936943 | Providing flexible matrix processors for performing neural network convolution in matrix-processor-based devices | Colin Beaton Verrilli, Mattheus Cornelis Antonius Adrianus Heddes, Koustav Bhattacharya, Robert S. Dreyer | 2021-03-02 |
| 10877951 | Network control software notification and invalidation of static entries | Claude Basso, Josep Cors, Venkatesh Janakiraman, Sze-Wa Lao, Sameer M. Shah +3 more | 2020-12-29 |
| 10838942 | Network control software notification and invalidation of static entries | Claude Basso, Josep Cors, Venkatesh Janakiraman, Sze-Wa Lao, Sameer M. Shah +3 more | 2020-11-17 |
| 10838862 | Memory controllers employing memory capacity compression, and related processor-based systems and methods | Mattheus Cornelis Antonius Adrianus Heddes, Colin Beaton Verrilli | 2020-11-17 |
| 10747501 | Providing efficient floating-point operations using matrix processors in processor-based systems | Mattheus Cornelis Antonius Adrianus Heddes, Robert S. Dreyer, Colin Beaton Verrilli, Koustav Bhattacharya | 2020-08-18 |
| 10725740 | Providing efficient multiplication of sparse matrices in matrix-processor-based devices | Mattheus Cornelis Antonius Adrianus Heddes, Robert S. Dreyer, Colin Beaton Verrilli, Koustav Bhattacharya | 2020-07-28 |
| 10541921 | Supporting access control list rules that apply to TCP segments belonging to ‘established’ connection | Claude Basso, Joseph A. Kirscht | 2020-01-21 |
| 10503661 | Providing memory bandwidth compression using compressed memory controllers (CMCs) in a central processing unit (CPU)-based system | Mattheus Cornelis Antonius Adrianus Heddes, Colin Beaton Verrilli | 2019-12-10 |
| 10467092 | Providing space-efficient storage for dynamic random access memory (DRAM) cache tags | Mattheus Cornelis Antonius Adrianus Heddes, Colin Beaton Verrilli | 2019-11-05 |
| 10419267 | Network control software notification with advance learning | Claude Basso, Josep Cors, Venkatesh Janakiraman, Sze-Wa Lao, Sameer M. Shah +3 more | 2019-09-17 |
| 10236917 | Providing memory bandwidth compression in chipkill-correct memory architectures | Luther James Blackwood, Mattheus Cornelis Antonius Adrianus Heddes, Michael R. Trombley, Colin Beaton Verrilli | 2019-03-19 |
| 10191850 | Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system | Colin Beaton Verrilli, Mattheus Cornelis Antonius Adrianus Heddes, Mark Anthony Rinaldi | 2019-01-29 |
| 10176096 | Providing scalable dynamic random access memory (DRAM) cache management using DRAM cache indicator caches | Mattheus Cornelis Antonius Adrianus Heddes, Colin Beaton Verrilli | 2019-01-08 |
| 10176090 | Providing memory bandwidth compression using adaptive compression in central processing unit (CPU)-based systems | Colin Beaton Verrilli, Mattheus Cornelis Antonius Adrianus Heddes | 2019-01-08 |
| 10152261 | Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based system | Colin Beaton Verrilli, Mattheus Cornelis Antonius Adrianus Heddes | 2018-12-11 |
| 10146693 | Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system | Colin Beaton Verrilli, Mattheus Cornelis Antonius Adrianus Heddes, Mark Anthony Rinaldi | 2018-12-04 |
| 10067706 | Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based system | Colin Beaton Verrilli, Mattheus Cornelis Antonius Adrianus Heddes | 2018-09-04 |
| 10055158 | Providing flexible management of heterogeneous memory systems using spatial quality of service (QoS) tagging in processor-based systems | Colin Beaton Verrilli, Carl A. Waldspurger, Mattheus Cornelis Antonius Adrianus Heddes, Koustav Bhattacharya | 2018-08-21 |
| 9860172 | Supporting access control list rules that apply to TCP segments belonging to ‘established’ connection | Claude Basso, Joseph A. Kirscht | 2018-01-02 |