Issued Patents All Time
Showing 1–25 of 122 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12380058 | Hardware-based image/video processing in machine learning-accelerator system-on-chip | Sandeep Pande, Satish Singh, Natarajan Vaidhyanathan, Vinay MURTHY | 2025-08-05 |
| 12340299 | Sparsity-based neural network mapping to computing units in a system-on-chip | Hee Jun Park | 2025-06-24 |
| 12165237 | Memory storage format for supporting machine learning acceleration | Natarajan Vaidhyanathan, Matthew Simpson, Geoffrey Carlton BERRY, Sandeep Pande | 2024-12-10 |
| 12155402 | Inline decompression | Natarajan Vaidhyanathan | 2024-11-26 |
| 11961007 | Split network acceleration architecture | Rashid Ahmed Akbar Attar, Raghavendar Bhavansikar | 2024-04-16 |
| 11449125 | Adaptive dynamic clock and voltage scaling | Matthew Severson | 2022-09-20 |
| 11362672 | Inline decompression | Natarajan Vaidhyanathan | 2022-06-14 |
| 11144368 | Providing self-resetting multi-producer multi-consumer semaphores in distributed processor-based systems | Natarajan Vaidhyanathan | 2021-10-12 |
| 11010313 | Method, apparatus, and system for an architecture for machine learning acceleration | Natarajan Vaidhyanathan, Rexford Hill | 2021-05-18 |
| 10936943 | Providing flexible matrix processors for performing neural network convolution in matrix-processor-based devices | Mattheus Cornelis Antonius Adrianus Heddes, Natarajan Vaidhyanathan, Koustav Bhattacharya, Robert S. Dreyer | 2021-03-02 |
| 10877951 | Network control software notification and invalidation of static entries | Claude Basso, Josep Cors, Venkatesh Janakiraman, Sze-Wa Lao, Sameer M. Shah +3 more | 2020-12-29 |
| 10838942 | Network control software notification and invalidation of static entries | Claude Basso, Josep Cors, Venkatesh Janakiraman, Sze-Wa Lao, Sameer M. Shah +3 more | 2020-11-17 |
| 10838862 | Memory controllers employing memory capacity compression, and related processor-based systems and methods | Mattheus Cornelis Antonius Adrianus Heddes, Natarajan Vaidhyanathan | 2020-11-17 |
| 10747501 | Providing efficient floating-point operations using matrix processors in processor-based systems | Mattheus Cornelis Antonius Adrianus Heddes, Natarajan Vaidhyanathan, Robert S. Dreyer, Koustav Bhattacharya | 2020-08-18 |
| 10725740 | Providing efficient multiplication of sparse matrices in matrix-processor-based devices | Mattheus Cornelis Antonius Adrianus Heddes, Robert S. Dreyer, Natarajan Vaidhyanathan, Koustav Bhattacharya | 2020-07-28 |
| 10503661 | Providing memory bandwidth compression using compressed memory controllers (CMCs) in a central processing unit (CPU)-based system | Mattheus Cornelis Antonius Adrianus Heddes, Natarajan Vaidhyanathan | 2019-12-10 |
| 10467092 | Providing space-efficient storage for dynamic random access memory (DRAM) cache tags | Natarajan Vaidhyanathan, Mattheus Cornelis Antonius Adrianus Heddes | 2019-11-05 |
| 10419267 | Network control software notification with advance learning | Claude Basso, Josep Cors, Venkatesh Janakiraman, Sze-Wa Lao, Sameer M. Shah +3 more | 2019-09-17 |
| 10236917 | Providing memory bandwidth compression in chipkill-correct memory architectures | Natarajan Vaidhyanathan, Luther James Blackwood, Mattheus Cornelis Antonius Adrianus Heddes, Michael R. Trombley | 2019-03-19 |
| 10191850 | Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system | Mattheus Cornelis Antonius Adrianus Heddes, Mark Anthony Rinaldi, Natarajan Vaidhyanathan | 2019-01-29 |
| 10176090 | Providing memory bandwidth compression using adaptive compression in central processing unit (CPU)-based systems | Natarajan Vaidhyanathan, Mattheus Cornelis Antonius Adrianus Heddes | 2019-01-08 |
| 10176096 | Providing scalable dynamic random access memory (DRAM) cache management using DRAM cache indicator caches | Natarajan Vaidhyanathan, Mattheus Cornelis Antonius Adrianus Heddes | 2019-01-08 |
| 10152261 | Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based system | Mattheus Cornelis Antonius Adrianus Heddes, Natarajan Vaidhyanathan | 2018-12-11 |
| 10146693 | Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system | Mattheus Cornelis Antonius Adrianus Heddes, Mark Anthony Rinaldi, Natarajan Vaidhyanathan | 2018-12-04 |
| 10067706 | Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based system | Mattheus Cornelis Antonius Adrianus Heddes, Natarajan Vaidhyanathan | 2018-09-04 |