Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12079149 | Presentation of direct accessed storage under a logical drive model | Thomas M. Slaight, Sivakumar Radhakrishnan, Mark A. Schmisseur, Pankaj Kumar, Saptarshi Mondal +9 more | 2024-09-03 |
| 11604746 | Presentation of direct accessed storage under a logical drive model | Thomas M. Slaight, Sivakumar Radhakrishnan, Mark A. Schmisseur, Pankaj Kumar, Saptarshi Mondal +9 more | 2023-03-14 |
| 9935653 | Enhanced cyclical redundancy check circuit based on galois-field arithmetic | Sivakumar Radhakrishnan, Kenneth C. Haren, Mark A. Schmisseur | 2018-04-03 |
| 9417821 | Presentation of direct accessed storage under a logical drive model | Thomas M. Slaight, Sivakumar Radhakrishnan, Mark A. Schmisseur, Pankaj Kumar, Saptarshi Mondal +9 more | 2016-08-16 |
| 9141469 | Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic | Sivakumar Radhakrishnan, Mark A. Schmisseur, Kenneth C. Haren, Thomas C. Brown, Pankaj Kumar +2 more | 2015-09-22 |
| 8850250 | Integration of processor and input/output hub | Lily P. Looi, Stephan Jourdan, Selim Bilgin, Anant Deval, Srikanth Srinivasan | 2014-09-30 |
| 8812878 | Limiting false wakeups of computing device components coupled via links | Srikanth Srinivasan, Bruce A. Tennant, Dmitry Petrov | 2014-08-19 |
| 8782456 | Dynamic and idle power reduction sequence using recombinant clock and power gating | Srikanth Srinivasan, Sivakumar Radhakrishnan, Stephan Jourdan, Lily P. Looi | 2014-07-15 |
| 8607129 | Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic | Sivakumar Radhakrishnan, Mark A. Schmisseur, Kenneth C. Haren, Thomas C. Brown, Pankaj Kumar +2 more | 2013-12-10 |
| 8352764 | Dynamic squelch detection power control | Sivakumar Radhakrishnan, Bruce A. Tennant, Jasper Balraj, Altug Koker | 2013-01-08 |
| 8275560 | Power measurement techniques of a system-on-chip (SOC) | Sivakumar Radhakrishnan, Stephan Jourdan, Lily P. Looi, Yi-Feng Liu | 2012-09-25 |
| 7500029 | Maximal length packets | Sivakumar Radhakrishnan, Siva Balasubramanian, Suneeta Sah | 2009-03-03 |
| 7386643 | Mechanism to guarantee forward progress for incoming coherent input/output (I/O) transactions for caching I/O agent on address conflict with processor transactions | Stanley S. Kulick, Rajesh S. Pamujula | 2008-06-10 |
| 7065596 | Method and apparatus to resolve instruction starvation | S. Steven Kulick, Rajee Ram, Rami Naqib | 2006-06-20 |
| 6832268 | Mechanism to guarantee forward progress for incoming coherent input/output (I/O) transactions for caching I/O agent on address conflict with processor transactions | Stanley S. Kulick, Rajesh S. Pamujula | 2004-12-14 |
| 6826619 | Method and apparatus for preventing starvation in a multi-node architecture | Manoj Khare, Akhilesh Kumar | 2004-11-30 |
| 6622215 | Mechanism for handling conflicts in a multi-node computer architecture | Manoj Khare, Akhilesh Kumar, Lily P. Looi | 2003-09-16 |
| 6298420 | Coherent variable length reads from system memory | Suresh Chittor, Chih-Cheh Chen, Jonathan Spitz | 2001-10-02 |
| 6134632 | Controller that supports data merging utilizing a slice addressable memory array | Lily P. Looi, John A. Urbanski, Christopher Van Beek | 2000-10-17 |
| 6061764 | Coherent variable length reads which implicates multiple cache lines by a memory controller connected to a serial and a pipelined bus utilizing a plurality of atomic transactions | Suresh Chittor, Chih-Cheh Chen, Jonathan Spitz | 2000-05-09 |
| 5996038 | Individually resettable bus expander bridge mechanism | Lily P. Looi, James A. Sutton | 1999-11-30 |