Issued Patents All Time
Showing 25 most recent of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11029744 | System, apparatus and method for controlling a processor based on effective stress information | Efraim Rotem, Esfir Natanzon, Doron Rajwan, Eliezer Weissmann, Dorit Shapira +2 more | 2021-06-08 |
| 10949356 | Fast page fault handling process implemented on persistent memory | James A. Boyd, Robert J. Royer, Jr., Gary C. Chow, Zvika Greenfield, Chia-Hung S. Kuo +1 more | 2021-03-16 |
| 10496152 | Power control techniques for integrated PCIe controllers | Bryan L. Spry, Shaun M. Conrad | 2019-12-03 |
| 10241952 | Throttling integrated link | Ravi Rajwar, Robert Mayer, Stephan Jourdan | 2019-03-26 |
| 9952643 | Device power management state transition latency advertisement for faster boot time | Mahesh Wagh | 2018-04-24 |
| 9952644 | Device power management state transition latency advertisement for faster boot time | Mahesh Wagh | 2018-04-24 |
| 9910814 | Method, apparatus and system for single-ended communication of transaction layer packets | Bryan L. Spry, Su Wei Lim, Mikal C. Hunsaker, Rohit Verma, Ronald W. Swartz +2 more | 2018-03-06 |
| 9537665 | Method, apparatus, and system for enabling platform power states | Selim Bilgin, Jeffrey C. Swanson | 2017-01-03 |
| 9146610 | Throttling integrated link | Ravi Rajwar, Robert Mayer, Stephan Jourdan | 2015-09-29 |
| 9021156 | Integrating intellectual property (IP) blocks into a processor | Prashanth Nimmala, Robert Greiner, Rupin H. Vakharwala, Marcus W. Song, James A. Beavens +2 more | 2015-04-28 |
| 8850250 | Integration of processor and input/output hub | Stephan Jourdan, Selim Bilgin, Sin S. Tan, Anant Deval, Srikanth Srinivasan | 2014-09-30 |
| 8782456 | Dynamic and idle power reduction sequence using recombinant clock and power gating | Sin S. Tan, Srikanth Srinivasan, Sivakumar Radhakrishnan, Stephan Jourdan | 2014-07-15 |
| 8539260 | Method, apparatus, and system for enabling platform power states | Selim Bilgin, Jeffrey C. Swanson | 2013-09-17 |
| 8275560 | Power measurement techniques of a system-on-chip (SOC) | Sivakumar Radhakrishnan, Sin S. Tan, Stephan Jourdan, Yi-Feng Liu | 2012-09-25 |
| 7996625 | Method and apparatus for reducing memory latency in a cache coherent multi-node architecture | Manoj Khare, Faye A. Briggs, Akhilesh Kumar, Kai Cheng | 2011-08-09 |
| 7617329 | Programmable protocol to support coherent and non-coherent transactions in a multinode system | Tuan M. Quach, Kai Cheng | 2009-11-10 |
| 7383398 | Preselecting E/M line replacement technique for a snoop filter | Liqun Cheng, Kai Cheng, Faye A. Briggs | 2008-06-03 |
| 7376775 | Apparatus, system, and method to enable transparent memory hot plug/remove | Stanley Steven Kulick, Dean Mulla, Ashish Gupta, Keith Robert Pflederer, Shivnandan Kaushik +2 more | 2008-05-20 |
| 7234029 | Method and apparatus for reducing memory latency in a cache coherent multi-node architecture | Manoj Khare, Faye A. Briggs, Akhilesh Kumar, Kai Cheng | 2007-06-19 |
| 7167957 | Mechanism for handling explicit writeback in a cache coherent multi-node architecture | Manoj Khare, Akhilesh Kumar | 2007-01-23 |
| 7124252 | Method and apparatus for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system | Manoj Khare, Akhilesh Kumar, Kenneth C. Creta | 2006-10-17 |
| 7093079 | Snoop filter bypass | Tuan M. Quach, Kai Cheng | 2006-08-15 |
| 6976129 | Mechanism for handling I/O transactions with known transaction length to coherent memory in a cache coherent multi-node architecture | Kenneth C. Creta, Manoj Khare, Akhilesh Kumar | 2005-12-13 |
| 6971098 | Method and apparatus for managing transaction requests in a multi-node architecture | Manoj Khare, Akhilesh Kumar, Ioannis T. Schoinas | 2005-11-29 |
| 6859864 | Mechanism for initiating an implicit write-back in response to a read or snoop of a modified cache line | Manoj Khare, Akhilesh Kumar, Kenneth C. Creta | 2005-02-22 |