| 11029744 |
System, apparatus and method for controlling a processor based on effective stress information |
Efraim Rotem, Esfir Natanzon, Doron Rajwan, Eliezer Weissmann, Dorit Shapira +2 more |
2021-06-08 |
$26,946,000 |
| 10949356 |
Fast page fault handling process implemented on persistent memory |
James A. Boyd, Robert J. Royer, Jr., Gary C. Chow, Zvika Greenfield, Chia-Hung S. Kuo +1 more |
2021-03-16 |
$38,556,000 |
| 10496152 |
Power control techniques for integrated PCIe controllers |
Bryan L. Spry, Shaun M. Conrad |
2019-12-03 |
$19,496,000 |
| 10241952 |
Throttling integrated link |
Ravi Rajwar, Robert Mayer, Stephan Jourdan |
2019-03-26 |
$18,583,000 |
| 9952643 |
Device power management state transition latency advertisement for faster boot time |
Mahesh Wagh |
2018-04-24 |
$19,097,000 |
| 9952644 |
Device power management state transition latency advertisement for faster boot time |
Mahesh Wagh |
2018-04-24 |
$19,097,000 |
| 9910814 |
Method, apparatus and system for single-ended communication of transaction layer packets |
Bryan L. Spry, Su Wei Lim, Mikal C. Hunsaker, Rohit Verma, Ronald W. Swartz +2 more |
2018-03-06 |
$18,859,000 |
| 9537665 |
Method, apparatus, and system for enabling platform power states |
Selim Bilgin, Jeffrey C. Swanson |
2017-01-03 |
$8,191,000 |
| 9146610 |
Throttling integrated link |
Ravi Rajwar, Robert Mayer, Stephan Jourdan |
2015-09-29 |
$22,047,000 |
| 9021156 |
Integrating intellectual property (IP) blocks into a processor |
Prashanth Nimmala, Robert Greiner, Rupin H. Vakharwala, Marcus W. Song, James A. Beavens +2 more |
2015-04-28 |
|
| 8850250 |
Integration of processor and input/output hub |
Stephan Jourdan, Selim Bilgin, Sin S. Tan, Anant Deval, Srikanth Srinivasan |
2014-09-30 |
$16,330,000 |
| 8782456 |
Dynamic and idle power reduction sequence using recombinant clock and power gating |
Sin S. Tan, Srikanth Srinivasan, Sivakumar Radhakrishnan, Stephan Jourdan |
2014-07-15 |
$14,407,000 |
| 8539260 |
Method, apparatus, and system for enabling platform power states |
Selim Bilgin, Jeffrey C. Swanson |
2013-09-17 |
$13,720,000 |
| 8275560 |
Power measurement techniques of a system-on-chip (SOC) |
Sivakumar Radhakrishnan, Sin S. Tan, Stephan Jourdan, Yi-Feng Liu |
2012-09-25 |
$23,105,000 |
| 7996625 |
Method and apparatus for reducing memory latency in a cache coherent multi-node architecture |
Manoj Khare, Faye A. Briggs, Akhilesh Kumar, Kai Cheng |
2011-08-09 |
$24,223,000 |
| 7617329 |
Programmable protocol to support coherent and non-coherent transactions in a multinode system |
Tuan M. Quach, Kai Cheng |
2009-11-10 |
$23,460,000 |
| 7383398 |
Preselecting E/M line replacement technique for a snoop filter |
Liqun Cheng, Kai Cheng, Faye A. Briggs |
2008-06-03 |
$37,699,000 |
| 7376775 |
Apparatus, system, and method to enable transparent memory hot plug/remove |
Stanley Steven Kulick, Dean Mulla, Ashish Gupta, Keith Robert Pflederer, Shivnandan Kaushik +2 more |
2008-05-20 |
$25,766,000 |
| 7234029 |
Method and apparatus for reducing memory latency in a cache coherent multi-node architecture |
Manoj Khare, Faye A. Briggs, Akhilesh Kumar, Kai Cheng |
2007-06-19 |
$30,093,000 |
| 7167957 |
Mechanism for handling explicit writeback in a cache coherent multi-node architecture |
Manoj Khare, Akhilesh Kumar |
2007-01-23 |
$17,655,000 |
| 7124252 |
Method and apparatus for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system |
Manoj Khare, Akhilesh Kumar, Kenneth C. Creta |
2006-10-17 |
$12,433,000 |
| 7093079 |
Snoop filter bypass |
Tuan M. Quach, Kai Cheng |
2006-08-15 |
$13,533,000 |
| 6976129 |
Mechanism for handling I/O transactions with known transaction length to coherent memory in a cache coherent multi-node architecture |
Kenneth C. Creta, Manoj Khare, Akhilesh Kumar |
2005-12-13 |
$11,810,000 |
| 6971098 |
Method and apparatus for managing transaction requests in a multi-node architecture |
Manoj Khare, Akhilesh Kumar, Ioannis T. Schoinas |
2005-11-29 |
$29,558,000 |
| 6859864 |
Mechanism for initiating an implicit write-back in response to a read or snoop of a modified cache line |
Manoj Khare, Akhilesh Kumar, Kenneth C. Creta |
2005-02-22 |
$35,388,000 |
