Issued Patents All Time
Showing 26–35 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6842830 | Mechanism for handling explicit writeback in a cache coherent multi-node architecture | Manoj Khare, Akhilesh Kumar | 2005-01-11 |
| 6810467 | Method and apparatus for centralized snoop filtering | Manoj Khare, Faye A. Briggs, Kai Cheng | 2004-10-26 |
| 6772298 | Method and apparatus for invalidating a cache line without data return in a multi-node architecture | Manoj Khare, Akhilesh Kumar, Ken Creta, Robert T. George, Michel Cekleov | 2004-08-03 |
| 6622215 | Mechanism for handling conflicts in a multi-node computer architecture | Manoj Khare, Akhilesh Kumar, Sin S. Tan | 2003-09-16 |
| 6615319 | Distributed mechanism for resolving cache coherence conflicts in a multi-node computer architecture | Manoj Khare, Akhilesh Kumar, Faye A. Briggs | 2003-09-02 |
| 6195722 | Method and apparatus for deferring transactions on a host bus having a third party agent | Rajee Ram, Suresh Chittor, David R. Jackson | 2001-02-27 |
| 6134632 | Controller that supports data merging utilizing a slice addressable memory array | Sin S. Tan, John A. Urbanski, Christopher Van Beek | 2000-10-17 |
| 5996038 | Individually resettable bus expander bridge mechanism | Sin S. Tan, James A. Sutton | 1999-11-30 |
| 5987552 | Bus protocol for atomic transactions | Suresh Chittor, Suvansh Krishan Kapur | 1999-11-16 |
| 5930486 | Method and device for gracious arbitration of access to a computer system resource | Nitin Y. Borkar, Frank Verhoorn | 1999-07-27 |