Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11188467 | Multi-level system memory with near memory capable of storing compressed cache lines | Israel Diamand, Alaa R. Alameldeen, Sreenivas Subramoney, Supratik Majumder, Srinivas Santosh Kumar MADUGULA +2 more | 2021-11-30 |
| 11036412 | Dynamically changing between latency-focused read operation and bandwidth-focused read operation | Sahar Khalili, Sowmiya Jayachandran, Robert J. Royer, Jr., Dimpesh Patel | 2021-06-15 |
| 10949356 | Fast page fault handling process implemented on persistent memory | James A. Boyd, Robert J. Royer, Jr., Lily P. Looi, Gary C. Chow, Chia-Hung S. Kuo +1 more | 2021-03-16 |
| 10915453 | Multi level system memory having different caching structures and memory controller that supports concurrent look-up into the different caching structures | Israel Diamand, Julius Mandelblat, Asaf Rubinstein | 2021-02-09 |
| 10678706 | Cache memory with scrubber logic | Eshel Serlin, Asaf Rubinstein, Eli Abadi | 2020-06-09 |
| 10657058 | Interleaved cache controllers with shared metadata and related devices and systems | Daniel Greenspan | 2020-05-19 |
| 10558570 | Concurrent accesses of asymmetrical memory sources | Nadav Bonen, Randy B. Osborne | 2020-02-11 |
| 10304418 | Operating system transparent system memory abandonment | Daniel Greenspan, Randy B. Osborne, Israel Diamand, Asaf Rubinstein | 2019-05-28 |
| 10241916 | Sparse superline removal | Zeshan A. Chishti, Israel Diamand | 2019-03-26 |
| 10210925 | Row hammer refresh command | Kuljit S. Bains, John B. Halbert, Christopher P. Mozak, Theodore Z. Schoenborn | 2019-02-19 |
| 10204047 | Memory controller for multi-level system memory with coherency unit | Israel Diamand, Nir Misgav, Aravindh Anantaraman | 2019-02-12 |
| 10176099 | Using data pattern to mark cache lines as invalid | Jayesh Gaur, Supratik Majumder, Israel Diamand | 2019-01-08 |
| 9865326 | Row hammer refresh command | Kuljit S. Bains, John B. Halbert, Christopher P. Mozak, Theodore Z. Schoenborn | 2018-01-09 |
| 9767041 | Managing sectored cache | Aravindh Anantaraman, Israel Diamand, Anant Vithal Nori, Pradeep Ramachandran, Nir Misgav | 2017-09-19 |
| 9747971 | Row hammer refresh command | Kuljit S. Bains, John B. Halbert, Christopher P. Mozak, Theodore Z. Schoenborn | 2017-08-29 |
| 9734079 | Hybrid exclusive multi-level memory architecture with memory management | Dannie Gerrit Feekes, Shlomo Raikin, Blaise Fanning, Joydeep Ray, Julius Mandelblat +3 more | 2017-08-15 |
| 9582430 | Asymmetric set combined cache | Nadav Bonen, Israel Diamand | 2017-02-28 |
| 9424198 | Method, system and apparatus including logic to manage multiple memories as a unified exclusive memory | Shlomo Raikin | 2016-08-23 |
| 9418013 | Selective prefetching for a sectored cache | Aravindh Anantaraman, Anant Vithal Nori, Julius Mandelblat | 2016-08-16 |
| 9251885 | Throttling support for row-hammer counters | Tomer Levy | 2016-02-02 |
| 9236110 | Row hammer refresh command | Kuljit S. Bains, John B. Halbert, Christopher P. Mozak, Theodore Z. Schoenborn | 2016-01-12 |
| 9117544 | Row hammer refresh command | Kuljit S. Bains, John B. Halbert, Christopher P. Mozak, Theodore Z. Schoenborn | 2015-08-25 |
| 9076019 | Method and apparatus for memory encryption with integrity check and protection against replay attacks | Shay Gueron, Uday Savagaonkar, Francis X. McKeen, Carlos V. Rozas, David M. Durham +4 more | 2015-07-07 |
| 9030903 | Method, apparatus and system for providing a memory refresh | Kuljit S. Bains, John B. Halbert, Suneeta Sah | 2015-05-12 |
| 9026725 | Training for command/address/control/clock delays under uncertain initial conditions and for mapping swizzled data to command/address signals | Alexey Kostinsky, Christopher P. Mozak, Pavel Konev, Olga Fomenko | 2015-05-05 |