Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
DG

Daniel Greenspan — 30 Patents

Intel: 17 patents #2,442 of 30,777Top 8%
WARF: 8 patents #189 of 4,123Top 5%
JMJohns Hopkins University School Of Medicine: 1 patents #129 of 255Top 55%
Pfizer: 1 patents #3,022 of 5,153Top 60%
Cisco: 1 patents #7,948 of 13,007Top 65%
Overall (All Time): #121,623 of 4,157,543Top 3%
30 Patents All Time
Daniel Greenspan has been granted 30 US patents while listed as an inventor at Intel. The first was granted in 1999 and the most recent in April 2022. Daniel Greenspan ranks #121,623 of 4,157,543 US inventors in our database (top 2.9%). Patent records list Daniel Greenspan in Jerusalem, WI, IL.

Issued Patents All Time

Showing 1–25 of 30 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11307021 Method and apparatus for indoor positioning Klonymus Sholom Lieberman 2022-04-19
10986294 Wide field of view optical module for linear sensor Klonymus Sholom Lieberman 2021-04-20
10718603 Method and apparatus for indoor positioning Klonymus Sholom Lieberman 2020-07-21
10657058 Interleaved cache controllers with shared metadata and related devices and systems Zvika Greenfield 2020-05-19 $31,576,000
10657070 Apparatus and method for shared least recently used (LRU) policy between multiple cache levels Blaise Fanning, Yoav Lossin, Asaf Rubinstein 2020-05-19 $31,576,000
10635593 Create page locality in cache controller cache allocation Anant Vithal Nori, Supratik Majumder, Yoav Lossin, Asaf Rubinstein 2020-04-28 $36,717,000
10511794 Wide field of view optical module for linear sensor Klonymus Sholom Lieberman 2019-12-17
10437732 Multi-level cache with associativity collision compensation 2019-10-08 $19,521,000
10437769 Transition-minimized low speed data transfer 2019-10-08 $19,521,000
10304418 Operating system transparent system memory abandonment Randy B. Osborne, Zvika Greenfield, Israel Diamand, Asaf Rubinstein 2019-05-28 $17,387,000
10153784 Use of error correcting code to carry additional data bits Asaf Rubinstein, Julius Mandelblat 2018-12-11 $24,515,000
10055360 Apparatus and method for shared least recently used (LRU) policy between multiple cache levels Blaise Fanning, Yoav Lossin, Asaf Rubinstein 2018-08-21 $25,621,000
9971691 Selevtive application of interleave based on type of data to be stored in memory Blaise Fanning 2018-05-15 $21,346,000
9846648 Create page locality in cache controller cache allocation Anant Vithal Nori, Supratik Majumder, Yoav Lossin, Asaf Rubinstein 2017-12-19 $19,551,000
9767042 Enhancing cache performance by utilizing scrubbed state indicators associated with cache entries Yoav Lossin 2017-09-19 $8,005,000
9559726 Use of error correcting code to carry additional data bits Asaf Rubinstein, Julius Mandelblat 2017-01-31 $9,360,000
9542325 Adjustable over-restrictive cache locking limit for improved overall performance Supratik Majumder 2017-01-10 $11,357,000
9514047 Apparatus and method to dynamically expand associativity of a cache memory Yoav Lossin, Blaise Fanning, Nagi Aboulenein, Marc Torrant 2016-12-06 $8,381,000
9436623 Run-time fabric reconfiguration Aviad Wertheimer 2016-09-06 $9,244,000
9396120 Adjustable over-restrictive cache locking limit for improved overall performance Supratik Majumder 2016-07-19 $7,217,000
8817937 System and method for performing timing control 2014-08-26 $15,304,000
7888313 Composition for treating a fibrotic disorder comprising an inhibitor of a BMP-1-like protein Yue Zhang, Gaoxiang Ge 2011-02-15
7680413 Optical network monitoring system and method 2010-03-16 $26,238,000
7572599 Metalloprotease activation of myostatin, and methods of modulating myostatin activity Se-Jin Lee, Alexandra C. McPherron, William N. Pappano, Neil M. Wolfman, Kathy Tomkinson 2009-08-11 $169,477,000
6759528 Mammalian pro-&agr;3(V) collagen chain genes Yasutada Imamura 2004-07-06