Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12056376 | Interconnected memory grid with bypassable units | Ron Schneider, Elad RAZ, Ilan TAYARI, Eyal Nagar | 2024-08-06 |
| 11644990 | Interconnected memory grid with bypassable units | Ron Schneider, Elad RAZ, Ilan TAYARI, Eyal Nagar | 2023-05-09 |
| 11269526 | Interconnected memory grid with bypassable units | Ron Schneider, Elad RAZ, Ilan TAYARI, Eyal Nagar | 2022-03-08 |
| 10657070 | Apparatus and method for shared least recently used (LRU) policy between multiple cache levels | Daniel Greenspan, Blaise Fanning, Asaf Rubinstein | 2020-05-19 |
| 10635593 | Create page locality in cache controller cache allocation | Daniel Greenspan, Anant Vithal Nori, Supratik Majumder, Asaf Rubinstein | 2020-04-28 |
| 10055360 | Apparatus and method for shared least recently used (LRU) policy between multiple cache levels | Daniel Greenspan, Blaise Fanning, Asaf Rubinstein | 2018-08-21 |
| 9846648 | Create page locality in cache controller cache allocation | Daniel Greenspan, Anant Vithal Nori, Supratik Majumder, Asaf Rubinstein | 2017-12-19 |
| 9767042 | Enhancing cache performance by utilizing scrubbed state indicators associated with cache entries | Daniel Greenspan | 2017-09-19 |
| 9514047 | Apparatus and method to dynamically expand associativity of a cache memory | Daniel Greenspan, Blaise Fanning, Nagi Aboulenein, Marc Torrant | 2016-12-06 |
| 8850258 | Calibration for source-synchronous high frequency bus synchronization schemes | Aviad Wertheimer | 2014-09-30 |