Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Nagi Aboulenein — 23 Patents

Intel: 14 patents #2,935 of 30,777Top 10%
ACAmpere Computing: 7 patents #3 of 94Top 4%
King City, OR: #2 of 16 inventorsTop 15%
Oregon: #1,851 of 28,073 inventorsTop 7%
Overall (All Time): #178,160 of 4,157,543Top 5%
23 Patents All Time
Nagi Aboulenein has been granted 23 US patents while listed as an inventor at Intel. The first was granted in 2004 and the most recent in November 2025. Nagi Aboulenein ranks #178,160 of 4,157,543 US inventors in our database (top 4.3%). Patent records list Nagi Aboulenein in King City, OR, US.

Issued Patents All Time

Showing 1–23 of 23 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12474848 Techniques for memory resource control using memory resource partitioning and monitoring Raymond S. Tetrick, Massimo Sutera, Shivnandan Kaushik 2025-11-18
12451206 Extending functionality of memory controllers using a loopback mode for testing in a processor-based device Massimo Sutera, Ravi Shankar Kumar, Kha Minh Huynh, Sandeep Brahmadathan, Anil Kumar Handenahalli Rajanna 2025-10-21
12314130 Parity protected memory blocks merged with error correction code (ECC) protected blocks in a codeword for increased memory utilization Massimo Sutera, Sandeep Brahmadathan 2025-05-27
12282064 Component die validation built-in self-test (VBIST) engine Sandeep Brahmadathan, Jared Eric Bendt, Kedar KARANDIKAR, Stephan Jourdan 2025-04-22
12204410 Integrated error correction code (ECC) and parity protection in memory control circuits for increased memory utilization Massimo Sutera, Sandeep Brahmadathan 2025-01-21
12182417 Address-range memory mirroring in a computer system, and related methods Sebastien Hily, Matthew Robert Erler, Shivnandan Kaushik, Donald Scott Phillips 2024-12-31
12159056 Extending functionality of memory controllers in a processor-based device Massimo Sutera, Sandeep Brahmadathan, Brian Thomas Chase, James Edward Casteel, Kha Minh Huynh +1 more 2024-12-03
11934263 Parity protected memory blocks merged with error correction code (ECC) protected blocks in a codeword for increased memory utilization Massimo Sutera, Sandeep Brahmadathan 2024-03-19
11586537 Method, apparatus, and system for run-time checking of memory tags in a processor-based system Benjamin Crawford Chaffin, Bret L. Toll, Jonathan Christopher Perry 2023-02-21
10621094 Coarse tag replacement Zhe Wang, Zeshan A. Chishti 2020-04-14 $33,667,000
10516439 Interference testing Alexey Kostinsky, Tomer Levy, Paul S. Cheses, Danny Naiger, Theodore Z. Schoenborn +2 more 2019-12-24 $26,956,000
10482947 Integrated error checking and correction (ECC) in byte mode memory devices Christopher E. Cox, Uksong Kang 2019-11-19 $26,843,000
9940984 Shared command address (C/A) bus for multiple memory channels MD Altaf Hossain, Jayapratap Bharathan 2018-04-10 $20,820,000
9851771 Dynamic power measurement and estimation to improve memory subsystem power performance Lawrence A Cooper, Justin J. Song, Xiuting C. Man, Christopher E. Cox, Rebecca Z. Loop 2017-12-26 $14,594,000
9722663 Interference testing Alexey Kostinsky, Tomer Levy, Paul S. Cheses, Danny Naiger, Theodore Z. Schoenborn +2 more 2017-08-01 $11,137,000
9514047 Apparatus and method to dynamically expand associativity of a cache memory Daniel Greenspan, Yoav Lossin, Blaise Fanning, Marc Torrant 2016-12-06 $8,381,000
9268724 Configuration of data strobes MD Altaf Hossain, Kevin J. Doran 2016-02-23 $10,383,000
8924651 Prefetch optimization in shared resource multi-core systems Perry P. Tang, Hemant G. Rotithor, Ryan Carlson 2014-12-30 $18,984,000
8683096 Configuration of data strobes MD Altaf Hossain, Kevin J. Doran 2014-03-25 $15,554,000
8443151 Prefetch optimization in shared resource multi-core systems Puqi Tang, Hemant G. Rotithor, Ryan Carlson 2013-05-14 $17,697,000
7127574 Method and apparatus for out of order memory scheduling Hemant G. Rotithor, Randy B. Osborne 2006-10-24 $13,658,000
6792496 Prefetching data for peripheral component interconnect devices Randy B. Osborne 2004-09-14 $15,917,000
6785793 Method and apparatus for memory access scheduling to reduce memory access latency Randy B. Osborne, Ram Huggahalli, Vamsee K. Madavarapu, Ken M. Crocker 2004-08-31 $18,815,000