Issued Patents All Time
Showing 25 most recent of 90 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12381160 | Memory device package with noise shielding | Jaejin Lee, Jun Liao, Xiang Li | 2025-08-05 |
| RE50373 | Reading from a mode register having different read and write timing | Bill Nale | 2025-04-08 |
| 12127361 | Modular memory devices | Leechung Yiu, Robert X. Jin, Zheng Qiu, Leonard Datus, Lizhi Jin | 2024-10-22 |
| 12080369 | Memory device with modular design and memory system comprising the same | Leechung Yiu, Robert X. Jin, Zheng Qiu, Leonard Datus, Lizhi Jin | 2024-09-03 |
| 11990172 | Refresh command control for host assist of row hammer mitigation | Bill Nale | 2024-05-21 |
| 11935623 | Apparatus for controlling access to a memory device and memory system comprising the same | Yibo Jiang, Leechung Yiu, Robert X. Jin, Lizhi Jin, Leonard Datus | 2024-03-19 |
| 11790976 | Periodic calibrations during memory device self refresh | Bill Nale | 2023-10-17 |
| 11688452 | Refresh command control for host assist of row hammer mitigation | Bill Nale | 2023-06-27 |
| 11675532 | Memory command that specifies one of multiple possible write data values where the write data is not transported over a memory data bus | Christopher P. Mozak | 2023-06-13 |
| 11662926 | Input/output (I/O) loopback function for I/O signaling testing | Dean-Dexter R. Eugenio, Arvind Kumar, John R. Goles | 2023-05-30 |
| 11380378 | Clock driver and memory device comprising the same | Yibo Jiang, Leechung Yiu, Lizhi Jin | 2022-07-05 |
| 11335395 | Applying chip select for memory device identification and power management control | Kuljit S. Bains, Christopher P. Mozak, James A. McCall, Akshith Vasanth, Bill Nale | 2022-05-17 |
| 11282561 | Refresh command control for host assist of row hammer mitigation | Bill Nale | 2022-03-22 |
| 11276453 | Periodic calibrations during memory device self refresh | Bill Nale | 2022-03-15 |
| 11226762 | Memory command that specifies one of multiple possible write data values where the write data is not transported over a memory data bus | Christopher P. Mozak | 2022-01-18 |
| 11093391 | Representing a cache line bit pattern via meta signaling | Saher Abu Rahme, Joydeep Ray | 2021-08-17 |
| 11074959 | DDR memory bus with a reduced data strobe signal preamble timespan | James A. McCall, Christopher P. Mozak, Yan Fu, Robert J. Friar, Hsien-Pao Yang | 2021-07-27 |
| 11061590 | Efficiently training memory device chip select control | Tonia G. Morris, Christopher P. Mozak | 2021-07-13 |
| 11042315 | Dynamically programmable memory test traffic router | Lakshminarayana Pappu, Navneet Dour, Asaf Rubinstein, Israel Diamand | 2021-06-22 |
| 10969979 | Input/output (I/O) loopback function for I/O signaling testing | Dean-Dexter R. Eugenio, Arvind Kumar, John R. Goles | 2021-04-06 |
| 10950288 | Refresh command control for host assist of row hammer mitigation | Bill Nale | 2021-03-16 |
| 10938161 | Snap-on electromagnetic interference (EMI)-shielding without motherboard ground requirement | Jaejin Lee, Jun Liao, Xiang Li | 2021-03-02 |
| 10923859 | Crosstalk reducing connector pin geometry | Jaejin Lee, Jun Liao, Xiang Li, George Vergis | 2021-02-16 |
| 10890931 | Memory module thermal management | Ishmael F. Santos, Corinne Hall | 2021-01-12 |
| 10839887 | Applying chip select for memory device identification and power management control | Kuljit S. Bains, Christopher P. Mozak, James A. McCall, Akshith Vasanth, Bill Nale | 2020-11-17 |