Issued Patents All Time
Showing 25 most recent of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12373287 | Distribution of error checking and correction (ECC) bits to allocate ECC bits for metadata | Rajat Agarwal, Wei-Pin Chen, James A. McCall | 2025-07-29 |
| 12347507 | Method and apparatus for memory chip row hammer threat backpressure signal and host side response | Kuljit S. Bains, Jongwon Lee, Sreenivas Mandava | 2025-07-01 |
| 12332739 | Buffer that supports burst transfers having parallel CRC and data transmissions | James A. McCall, Zibing Yang, Yanjie Zhu | 2025-06-17 |
| 12321634 | Double fetch for long burst length memory data transfer | Kuljit S. Bains | 2025-06-03 |
| RE50373 | Reading from a mode register having different read and write timing | Christopher E. Cox | 2025-04-08 |
| 12217787 | Apparatus, system and method to detect and improve an input clock performance of a memory device | Arvind Kumar, James A. McCall, John R. Goles, Dean-Dexter R. Eugenio | 2025-02-04 |
| 12190979 | Dynamic random access memory built-in self-test power fail mitigation | — | 2025-01-07 |
| 12164373 | Memory chip with per row activation count having error correction code protection | Kuljit S. Bains, Lawrence D. BLANKENBECKLER, Ronald ANDERSON, Jongwon Lee | 2024-12-10 |
| 12147698 | High performance memory module with reduced loading | George Vergis | 2024-11-19 |
| 12106818 | Power control of a memory device in connected standby state | Aiswarya M. Pious, Raji James, Phani Alaparthi, George Vergis, Konika Ganguly | 2024-10-01 |
| 11990172 | Refresh command control for host assist of row hammer mitigation | Christopher E. Cox | 2024-05-21 |
| 11837314 | Undo and redo of soft post package repair | Kuljit S. Bains, Wei-Pin Chen, Rajat Agarwal | 2023-12-05 |
| 11790976 | Periodic calibrations during memory device self refresh | Christopher E. Cox | 2023-10-17 |
| 11699471 | Synchronous dynamic random access memory (SDRAM) dual in-line memory module (DIMM) having increased per data pin bandwidth | Duane E. Galbi | 2023-07-11 |
| 11688452 | Refresh command control for host assist of row hammer mitigation | Christopher E. Cox | 2023-06-27 |
| 11335395 | Applying chip select for memory device identification and power management control | Christopher E. Cox, Kuljit S. Bains, Christopher P. Mozak, James A. McCall, Akshith Vasanth | 2022-05-17 |
| 11282561 | Refresh command control for host assist of row hammer mitigation | Christopher E. Cox | 2022-03-22 |
| 11276453 | Periodic calibrations during memory device self refresh | Christopher E. Cox | 2022-03-15 |
| 10997096 | Enumerated per device addressability for memory subsystems | Tonia G. Morris | 2021-05-04 |
| 10963404 | High bandwidth DIMM | James A. McCall, Rajat Agarwal, George Vergis | 2021-03-30 |
| 10950288 | Refresh command control for host assist of row hammer mitigation | Christopher E. Cox | 2021-03-16 |
| 10884958 | DIMM for a high bandwidth memory channel | Rajat Agarwal, Chong J. Zhao, James A. McCall, George Vergis | 2021-01-05 |
| 10884941 | Techniques to store data for critical chunk operations | — | 2021-01-05 |
| 10872011 | Internal error checking and correction (ECC) with extra system bits | Kuljit S. Bains, Rajat Agarwal | 2020-12-22 |
| 10839887 | Applying chip select for memory device identification and power management control | Christopher E. Cox, Kuljit S. Bains, Christopher P. Mozak, James A. McCall, Akshith Vasanth | 2020-11-17 |