Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
BN

Bill Nale — 64 Patents

Intel: 62 patents #460 of 30,777Top 2%
SSSk Hynix Nand Product Solutions: 1 patents #82 of 148Top 60%
Sony: 1 patents #17,321 of 25,231Top 70%
Livermore, CA: #17 of 2,185 inventorsTop 1%
California: #5,241 of 386,348 inventorsTop 2%
Overall (All Time): #34,494 of 4,157,543Top 1%
64 Patents All Time
Bill Nale has been granted 64 US patents while listed as an inventor at Intel. The first was granted in 2007 and the most recent in October 2025. Bill Nale ranks #34,494 of 4,157,543 US inventors in our database (top 0.83%). Patent records list Bill Nale in Livermore, CA, US.

Issued Patents All Time

Showing 1–25 of 64 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12443367 Perfect row hammer tracking with multiple count increments Kuljit S. Bains 2025-10-14
12373287 Distribution of error checking and correction (ECC) bits to allocate ECC bits for metadata Rajat Agarwal, Wei-Pin Chen, James A. McCall 2025-07-29
12347507 Method and apparatus for memory chip row hammer threat backpressure signal and host side response Kuljit S. Bains, Jongwon Lee, Sreenivas Mandava 2025-07-01
12332739 Buffer that supports burst transfers having parallel CRC and data transmissions James A. McCall, Zibing Yang, Yanjie Zhu 2025-06-17
12321634 Double fetch for long burst length memory data transfer Kuljit S. Bains 2025-06-03
RE50373 Reading from a mode register having different read and write timing Christopher E. Cox 2025-04-08
12217787 Apparatus, system and method to detect and improve an input clock performance of a memory device Arvind Kumar, James A. McCall, John R. Goles, Dean-Dexter R. Eugenio 2025-02-04
12190979 Dynamic random access memory built-in self-test power fail mitigation 2025-01-07
12164373 Memory chip with per row activation count having error correction code protection Kuljit S. Bains, Lawrence D. BLANKENBECKLER, Ronald ANDERSON, Jongwon Lee 2024-12-10 $13,394,000
12147698 High performance memory module with reduced loading George Vergis 2024-11-19 $25,575,000
12106818 Power control of a memory device in connected standby state Aiswarya M. Pious, Raji James, Phani Alaparthi, George Vergis, Konika Ganguly 2024-10-01 $20,560,000
11990172 Refresh command control for host assist of row hammer mitigation Christopher E. Cox 2024-05-21 $18,840,000
11837314 Undo and redo of soft post package repair Kuljit S. Bains, Wei-Pin Chen, Rajat Agarwal 2023-12-05
11790976 Periodic calibrations during memory device self refresh Christopher E. Cox 2023-10-17 $15,641,000
11699471 Synchronous dynamic random access memory (SDRAM) dual in-line memory module (DIMM) having increased per data pin bandwidth Duane E. Galbi 2023-07-11 $21,736,000
11688452 Refresh command control for host assist of row hammer mitigation Christopher E. Cox 2023-06-27 $18,721,000
11335395 Applying chip select for memory device identification and power management control Christopher E. Cox, Kuljit S. Bains, Christopher P. Mozak, James A. McCall, Akshith Vasanth 2022-05-17 $14,251,000
11282561 Refresh command control for host assist of row hammer mitigation Christopher E. Cox 2022-03-22 $16,833,000
11276453 Periodic calibrations during memory device self refresh Christopher E. Cox 2022-03-15 $18,336,000
10997096 Enumerated per device addressability for memory subsystems Tonia G. Morris 2021-05-04 $37,420,000
10963404 High bandwidth DIMM James A. McCall, Rajat Agarwal, George Vergis 2021-03-30 $32,599,000
10950288 Refresh command control for host assist of row hammer mitigation Christopher E. Cox 2021-03-16 $38,556,000
10884941 Techniques to store data for critical chunk operations 2021-01-05 $27,050,000
10884958 DIMM for a high bandwidth memory channel Rajat Agarwal, Chong J. Zhao, James A. McCall, George Vergis 2021-01-05 $27,050,000
10872011 Internal error checking and correction (ECC) with extra system bits Kuljit S. Bains, Rajat Agarwal 2020-12-22 $47,741,000