Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12367943 | Reference voltage adjustment per path for high speed memory signaling | Arvind Kumar, Dean-Dexter R. Eugenio | 2025-07-22 |
| 12332812 | Memory device manageability bus | George Vergis | 2025-06-17 |
| 12217787 | Apparatus, system and method to detect and improve an input clock performance of a memory device | Arvind Kumar, James A. McCall, Bill Nale, Dean-Dexter R. Eugenio | 2025-02-04 |
| 12204751 | Reference voltage training per path for high speed memory signaling | Arvind Kumar, Dean-Dexter R. Eugenio, Santhosh Muskula | 2025-01-21 |
| 11662926 | Input/output (I/O) loopback function for I/O signaling testing | Dean-Dexter R. Eugenio, Arvind Kumar, Christopher E. Cox | 2023-05-30 |
| 10969974 | Power-based dynamic adjustment of memory module bandwidth | George Vergis, Douglas Heymann, Dat Le | 2021-04-06 |
| 10969979 | Input/output (I/O) loopback function for I/O signaling testing | Dean-Dexter R. Eugenio, Arvind Kumar, Christopher E. Cox | 2021-04-06 |
| 10891243 | Memory bus MR register programming process | Tonia G. Morris, John V. Lovelace | 2021-01-12 |
| 10592445 | Techniques to access or operate a dual in-line memory module via multiple data channels | Bill Nale, Christopher E. Cox, Kuljit S. Bains, George Vergis, James A. McCall +3 more | 2020-03-17 |
| 10496309 | Input/output (I/O) loopback function for I/O signaling testing | Dean-Dexter R. Eugenio, Arvind Kumar, Christopher E. Cox | 2019-12-03 |
| 10380043 | Memory bus MR register programming process | Tonia G. Morris, John V. Lovelace | 2019-08-13 |
| 10146711 | Techniques to access or operate a dual in-line memory module via multiple data channels | Bill Nale, Kuljit S. Bains, George Vergis, Christopher E. Cox, James A. McCall +3 more | 2018-12-04 |