Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11722128 | Duty cycle correction system and low dropout (LDO) regulator based delay-locked loop (DLL) | Aaron Martin, Roger K. Cheng, Hari Venkatramani, Mozhgan Mansuri, Bryan K. Casper +8 more | 2023-08-08 |
| 11070200 | Duty cycle correction system and low dropout (LDO) regulator based delay-locked loop (DLL) | Aaron Martin, Roger K. Cheng, Hari Venkatramani, Mozhgan Mansuri, Bryan K. Casper +8 more | 2021-07-20 |
| 11042315 | Dynamically programmable memory test traffic router | Lakshminarayana Pappu, Christopher E. Cox, Asaf Rubinstein, Israel Diamand | 2021-06-22 |
| 10613955 | Platform debug and testing with secured hardware | Lakshminarayana Pappu, Christopher E. Cox | 2020-04-07 |
| 7751274 | Extended synchronized clock | Joe Salmon | 2010-07-06 |
| 7746135 | Wake-up circuit | Jacob Schneider, Harishankar Sridharan | 2010-06-29 |
| 7602859 | Calibrating integrating receivers for source synchronous protocol | Roger K. Cheng, Harishankar Sridharan, Hing Y. To | 2009-10-13 |
| 7432731 | Method and apparatus to calibrate DRAM on resistance (Ron) and on-die termination (ODT) values over process, voltage and temperature (PVT) variations | Kuljit S. Bains, Hany Fahmy, George Vergis, Christopher E. Cox | 2008-10-07 |
| 7403034 | PVT controller for programmable on die termination | Roger K. Cheng | 2008-07-22 |
| 7307900 | Method and apparatus for optimizing strobe to clock relationship | Joe Salmon, George Vergis | 2007-12-11 |
| 7020818 | Method and apparatus for PVT controller for programmable on die termination | Roger K. Cheng | 2006-03-28 |
| 7012451 | Slew rate at buffers by isolating predriver from driver | Adhiveeraraghavan Srikanth | 2006-03-14 |
| 7009894 | Dynamically activated memory controller data termination | Anoop Mukker, Zohar Bogin, Dave Freker | 2006-03-07 |
| 6617891 | Slew rate at buffers by isolating predriver from driver | Adhiveeraraghavan Srikanth | 2003-09-09 |
| 6563337 | Driver impedance control mechanism | — | 2003-05-13 |
| 6414539 | AC timings at the input buffer of source synchronous and common clock designs by making the supply for differential amplifier track the reference voltage | Adhiveeraraghavan Srikanth | 2002-07-02 |
| 6236250 | Circuit for independent power-up sequencing of a multi-voltage chip | Joseph H. Salmon | 2001-05-22 |