Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8595428 | Memory controller functionalities to support data swizzling | Kuljit S. Bains | 2013-11-26 |
| 8533538 | Method and apparatus for training a memory signal via an error signal of a memory | Santanu Chaudhuri, Kuljit S. Bains | 2013-09-10 |
| 8392796 | Reliability, availability, and serviceability solution for memory technology | Kuljit S. Bains | 2013-03-05 |
| 8132074 | Reliability, availability, and serviceability solutions for memory technology | Kuljit S. Bains | 2012-03-06 |
| 7194559 | Slave I/O driver calibration using error-nulling master reference | Hing Y. To | 2007-03-20 |
| 7117401 | Method and apparatus for optimizing timing for a multi-drop bus | Hing Y. To | 2006-10-03 |
| 6973603 | Method and apparatus for optimizing timing for a multi-drop bus | Hing Y. To | 2005-12-06 |
| 6941484 | Synthesis of a synchronization clock | Hing Y. To, Michael W. Williams | 2005-09-06 |
| 6885959 | Circuit and method for calibrating DRAM pullup Ron to pulldown Ron | Hing Y. To | 2005-04-26 |
| 6421801 | Testing IO timing in a delay locked system using separate transmit and receive loops | John Maddux | 2002-07-16 |
| 6381722 | Method and apparatus for testing high speed input paths | John Maddux | 2002-04-30 |
| 6260105 | Memory controller with a plurality of memory address buses | Mike WILLIAMS, Jasmin Ajanovic | 2001-07-10 |
| 6236250 | Circuit for independent power-up sequencing of a multi-voltage chip | Navneet Dour | 2001-05-22 |
| 6195759 | Method and apparatus for operating a synchronous strobe bus | — | 2001-02-27 |
| 5892377 | Method and apparatus for reducing leakage currents in an I/O buffer | Robert J. Johnston | 1999-04-06 |
| 5574857 | Error detection circuit for power up initialization of a memory array | K. K. Ramakrishnan, Randy C. Steele | 1996-11-12 |
| 5533196 | Method and apparatus for testing for a sufficient write voltage level during power up of a SRAM array | — | 1996-07-02 |
| 5490109 | Method and apparatus for preventing over-erasure of flash EEPROM memory devices | — | 1996-02-06 |
| 5379249 | UPROM programming protect circuit | — | 1995-01-03 |
| 5298807 | Buffer circuitry for transferring signals from TTL circuitry to dual range CMOS circuitry | Clyde L. Johnson | 1994-03-29 |
| 5257221 | Apparatus for selecting mumber of wait states in a burst EPROM architecture | David A. Leak, Robert E. Larsen | 1993-10-26 |
| 5243700 | Port expander architecture for mapping a first set of addresses to external memory and mapping a second set of addresses to an I/O port | Robert E. Larsen, Khandker N. Quader, Terry L. Kendall | 1993-09-07 |
| 5216289 | Asynchronous reset scheme for ultra-low noise port tri-state output driver circuit | Michael Hahn, Jeffery D. Wilson | 1993-06-01 |
| 5170073 | Ultra-low noise port output driver circuit | Michael Hahn, Robert E. Larsen | 1992-12-08 |
| 5159672 | Burst EPROM architecture | Robert E. Larsen, David A. Leak, Kurt B. Robinson, Dhiraj Parmar | 1992-10-27 |