Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12147286 | Power and thermal management in a solid state drive | Romesh Trivedi, Suresh Nagarajan | 2024-11-19 |
| 12014081 | Host managed buffer to store a logical-to physical address table for a solid state drive | Suresh Nagarajan, Shankar Natarajan, Romesh Trivedi | 2024-06-18 |
| 11625084 | Method of optimizing device power and efficiency based on host-controlled hints prior to low-power entry for blocks and components on a PCI express device | Kuan Hau Tan, Ang Li, Wai Ben Lin, Arash Talebi | 2023-04-11 |
| 11481352 | Method for interface initialization using bus turn-around | Zhenyu Zhu, Nobuyuki Suzuki, Daniel Nemiroff, David W. Vogel | 2022-10-25 |
| 11048659 | Method for interface initialization using bus turn-around | Zhenyu Zhu, Nobuyuki Suzuki, Daniel Nemiroff, David W. Vogel | 2021-06-29 |
| 10649484 | Dynamic adaptive clocking for non-common-clock interfaces | Eng Hun Ooi, Robert J. Royer, Jr., Brian R. McFarlane | 2020-05-12 |
| 10345885 | Power control of a memory device through a sideband channel of a memory bus | Brian R. McFarlane, Robert J. Royer, Jr., Eng Hun Ooi, Ritesh B. Trivedi | 2019-07-09 |
| 10185696 | Method for interface initialization using bus turn-around | Zhenyu Zhu, Nobuyuki Suzuki, Daniel Nemiroff, David W. Vogel | 2019-01-22 |
| 10168760 | Power management of user interfaces with coordinated ultra-low power states | Zhenyu Zhu, Daniel Nemiroff, Nobuyuki Suzuki, David W. Vogel | 2019-01-01 |
| 9952619 | Dynamic adaptive clocking for non-common-clock interfaces | Eng Hun Ooi, Robert J. Royer, Jr., Brian R. McFarlane | 2018-04-24 |
| 9904650 | Configuring a remote M-PHY | Karthi R. Vadivelu, Sridharan Ranganathan, Satheesh Chellappan | 2018-02-27 |
| 9280510 | Inter-chip communications with link layer interface and protocol adaptor | Sridharan Ranganathan, David J. Harriman, Satheesh Chellappan, Karthi R. Vadivelu, Shalini Sharma +1 more | 2016-03-08 |
| 9092367 | Configuring a remote M-PHY | Karthi R. Vadivelu, Sridharan Ranganathan, Satheesh Chellappan | 2015-07-28 |
| 8972646 | Superspeed inter-chip interface | Sridharan Ranganathan, David J. Harriman, Satheesh Chellappan, Karthi R. Vadivelu, Shalini Sharma +1 more | 2015-03-03 |
| 7797492 | Method and apparatus for dedicating cache entries to certain streams for performance optimization | Zohar Bogin, Tuong Trieu, Aditya Navale | 2010-09-14 |
| 7612780 | Optimized memory addressing | David E. Freker, Aditya Sreenivas, Zohar Bogin, Tuong Trieu | 2009-11-03 |
| 7230627 | Optimized memory addressing | David E. Freker, Aditya Sreenivas, Zohar Bogin, Tuong Trieu | 2007-06-12 |
| 7181605 | Deterministic shut down of memory devices in response to a system warm reset | Zohar Bogin, Surya Kareenahalli, David Sastry, Tuong Trieu | 2007-02-20 |
| 7058752 | Hardware detected command-per-clock | Suryaprasad Kareenahalli, Zohar Bogin | 2006-06-06 |
| 7009894 | Dynamically activated memory controller data termination | Zohar Bogin, Dave Freker, Navneet Dour | 2006-03-07 |
| 6868469 | Data bridge and bridging | Joseph A. Bennett, Mikal C. Hunsaker, Adit Tarmaster | 2005-03-15 |