Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12147286 | Power and thermal management in a solid state drive | Anoop Mukker, Suresh Nagarajan | 2024-11-19 |
| 12019558 | Logical to physical address indirection table in a persistent memory in a solid state drive | Suresh Nagarajan, Scott Crippin, Sahar Khalili, Shankar Natarajan | 2024-06-25 |
| 12014081 | Host managed buffer to store a logical-to physical address table for a solid state drive | Suresh Nagarajan, Anoop Mukker, Shankar Natarajan | 2024-06-18 |
| 10909040 | Adaptive calibration of nonvolatile memory channel based on platform power management state | Shankar Natarajan | 2021-02-02 |
| 10877686 | Mass storage device with host initiated buffer flushing | Shankar Natarajan, Suresh Nagarajan, Sriram Natarajan | 2020-12-29 |
| 10650886 | Block management for dynamic single-level cell buffers in storage devices | Shankar Natarajan, Sriram Natarajan, Suresh Nagarajan, Ramkarthik Ganesan, Arun S. Athreya | 2020-05-12 |
| 10229735 | Block management for dynamic single-level cell buffers in storage devices | Shankar Natarajan, Sriram Natarajan, Suresh Nagarajan, Ramkarthik Ganesan, Arun S. Athreya | 2019-03-12 |
| 7114087 | Method to detect a temperature change by a thermal monitor and compensating for process, voltage, temperature effects caused by the temperature change | Christine Watnik, Zohar Bogin, Buderya Acharya | 2006-09-26 |
| 6915407 | Method and apparatus for a low latency source-synchronous address receiver for a host system bus in a memory controller | Srinivasan T. Rajappa, Rajagopal Subramanian, Zohar Bogin, Serafin E. Garcia | 2005-07-05 |
| 6748513 | Method and apparatus for a low latency source-synchronous address receiver for a host system bus in a memory controller | Srinivasan T. Rajappa, Rajagopal Subramanian, Zohar Bogin, Serafin E. Garcia | 2004-06-08 |
| 6745337 | Glitch detection circuit for outputting a signal indicative of a glitch on a strobe signal and initializing an edge detection circuit in response to a control signal | Srinivasan T. Rajappa | 2004-06-01 |
| 6166563 | Method and apparatus for dual mode output buffer impedance compensation | Andrew M. Volk, Jennefer Asperheim, Hou-Sheng Lin | 2000-12-26 |