Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for a low latency source-synchronous address receiver for a host system bus in a memory controller

Method and apparatus for a low latency source-synchronous address receiver for a host system bus in a memory controller

US Patent 6915407 · Granted Jul 5, 2005

Estimated economic value: $31,328,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Power and thermal management in a solid state drive2024
Logical to physical address indirection table in a persistent memory in a solid 2024
Host managed buffer to store a logical-to physical address table for a solid sta2024
Adaptive calibration of nonvolatile memory channel based on platform power manag2021
Mass storage device with host initiated buffer flushing2020
Block management for dynamic single-level cell buffers in storage devices2020
Block management for dynamic single-level cell buffers in storage devices2019
Providing multiple virtual device controllers by redirecting an interrupt from a2016
Methods and apparatuses for securing playback content2015
Paging instruction for a virtualization engine to local storage2012
Method and apparatus for dedicating cache entries to certain streams for perform2010
Stream under-run/over-run recovery2010