| 9237000 |
Transceiver clock architecture with transmit PLL and receive slave delay lines |
Aaron Martin, Hon-Mo Law, Ying Zhou, Derek M. Conrow |
2016-01-12 |
| 8495330 |
Method and apparatus for interfacing with heterogeneous dual in-line memory modules |
George Vergis, Kuljit S. Bains |
2013-07-23 |
| 8468433 |
Optimizing the size of memory devices used for error correction code storage |
Kuljit S. Bains |
2013-06-18 |
| 8458507 |
Bus frequency adjustment circuitry for use in a dynamic random access memory device |
Kuljit S. Bains |
2013-06-04 |
| 8108761 |
Optimizing the size of memory devices used for error correction code storage |
Kuljit S. Bains |
2012-01-31 |
| 7954001 |
Nibble de-skew method, apparatus, and system |
Aaron Martin, Hing Y. To, Mamun Ur Rashid |
2011-05-31 |
| 7751274 |
Extended synchronized clock |
Navneet Dour |
2010-07-06 |
| 7555670 |
Clocking architecture using a bidirectional clock port |
Ravindran Mohanavelu, Aaron Martin, Dawson W. Kesling, Mamun Ur Rashid |
2009-06-30 |
| 7459938 |
Method and apparatus for power efficient and scalable memory interface |
Hing Y. To |
2008-12-02 |
| 7447929 |
Countering power resonance |
James A. McCall |
2008-11-04 |
| 7401246 |
Nibble de-skew method, apparatus, and system |
Aaron Martin, Hing Y. To, Mamun Ur Rashid |
2008-07-15 |
| 7324403 |
Latency normalization by balancing early and late clocks |
Hing Y. To, Mamun Ur Rashid |
2008-01-29 |
| 7307900 |
Method and apparatus for optimizing strobe to clock relationship |
Navneet Dour, George Vergis |
2007-12-11 |
| 7243176 |
Method and apparatus for power efficient and scalable memory interface |
Hing Y. To |
2007-07-10 |
| 6662305 |
Fast re-synchronization of independent domain clocks after powerdown to enable fast system start-up |
Andrew M. Volk |
2003-12-09 |