Issued Patents All Time
Showing 25 most recent of 90 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11826646 | System and method for providing one or more services using an augmented reality display | — | 2023-11-28 |
| 10162373 | Variation immune on-die voltage droop detector | Luca Ravezzi, Alfred Yeung, Hamid Partovi | 2018-12-25 |
| 10145868 | Self-referenced on-die voltage droop detector | Luca Ravezzi, Alfred Yeung, Hamid Partovi | 2018-12-04 |
| 9711189 | On-die input reference voltage with self-calibrating duty cycle correction | Bonnie I. Wang, Chiakang Sung, Xiaobao Wang, Joseph Huang, Khai Nguyen +1 more | 2017-07-18 |
| 9166589 | Multiple data rate interface architecture | Philip Pan, Chiakang Sung, Joseph Huang, Bonnie I. Wang | 2015-10-20 |
| 9166596 | Memory interface circuitry with improved timing margins | Warren Nordyke, Sean Shau-Tu Lu, Ee Mei Ooi, Khai Nguyen | 2015-10-20 |
| 9158873 | Circuit design technique for DQS enable/disable calibration | Joseph Huang, Sean Shau-Tu Lu, Pradeep Nagarajan, Chiakang Sung | 2015-10-13 |
| 9106230 | Input-output circuitry for integrated circuits | Bonnie I. Wang, Warren Nordyke, Weiqi Ding | 2015-08-11 |
| 9059716 | Digital PVT compensation for delay chain | Pradeep Nagarajan, Sean Shau-Tu Lu, Chiakang Song, Joseph Huang | 2015-06-16 |
| 8922264 | Methods and apparatus for clock tree phase alignment | Warren Nordyke, Sean Shau-Tu Lu, Weiqi Ding | 2014-12-30 |
| 8847626 | Circuits and methods for providing clock signals | Warren Nordyke, Pradeep Nagarajan, James Lin, Weiqi Ding | 2014-09-30 |
| 8816743 | Clock structure with calibration circuitry | Sean Shau-Tu Lu, Kin Hong Au, Khai Nguyen | 2014-08-26 |
| 8787097 | Circuit design technique for DQS enable/disable calibration | Joseph Huang, Sean Shau-Tu Lu, Pradeep Nagarajan, Chiakang Sung | 2014-07-22 |
| 8779754 | Method and apparatus for minimizing skew between signals | Joseph Huang, Chiakang Sung, Eric Choong-Yin Chang, Peter Boyle, Adam Wright | 2014-07-15 |
| 8723575 | Configurable delay circuitry with compensated delay | Ee Mei Ooi, Kin Hong Au, Ket Chiew Sia, Joseph Huang | 2014-05-13 |
| 8680905 | Digital PVT compensation for delay chain | Pradeep Nagarajan, Sean Shau-Tu Lu, Chiakang Sung, Joseph Huang | 2014-03-25 |
| 8671303 | Write-leveling implementation in programmable logic devices | Bonnie I. Wang, Chiakang Sung, Joseph Huang, Michael H. M. Chu | 2014-03-11 |
| 8624647 | Duty cycle correction circuit for memory interfaces in integrated circuits | Joseph Huang, Pradeep Nagarajan, Chiakang Sung | 2014-01-07 |
| 8593195 | High performance memory interface circuit architecture | Joseph Huang, Chiakang Sung, Philip Pan, Andy L. Lee, Brian Johnson | 2013-11-26 |
| 8575957 | Multiple data rate interface architecture | Philip Pan, Chiakang Sung, Joseph Huang, Bonnie I. Wang | 2013-11-05 |
| 8565034 | Variation compensation circuitry for memory interface | Sean Shau-Tu Lu, Joseph Huang, Pradeep Nagarajan, Chiakang Sung | 2013-10-22 |
| 8305121 | High-performance memory interface circuit architecture | Joseph Huang, Chiakang Sung, Philip Pan, Andy L. Lee, Brian Johnson | 2012-11-06 |
| 8237475 | Techniques for generating PVT compensated phase offset to improve accuracy of a locked loop | Pradeep Nagarajan, Sean Shau-Tu Lu, Chiakang Sung, Joseph Huang | 2012-08-07 |
| 8159277 | Techniques for providing multiple delay paths in a delay circuit | Pradeep Nagarajan, Chiakang Sung, Joseph Huang | 2012-04-17 |
| 8130016 | Techniques for providing reduced duty cycle distortion | Pradeep Nagarajan, Chiakang Sung, Joseph Huang | 2012-03-06 |