MC

Michael H. M. Chu

IN Intel: 14 patents #2,910 of 30,777Top 10%
Overall (All Time): #352,283 of 4,157,543Top 9%
14
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8671303 Write-leveling implementation in programmable logic devices Yan Chong, Bonnie I. Wang, Chiakang Sung, Joseph Huang 2014-03-11
8122275 Write-leveling implementation in programmable logic devices Yan Chong, Bonnie I. Wang, Chiakang Sung, Joseph Huang 2012-02-21
7990783 Postamble timing for DDR memories Philip Clarke, Andrew Bellis, Yan Chong, Joseph Huang 2011-08-02
7990786 Read-leveling implementations for DDR3 applications on an FPGA Joseph Huang, Chiakang Sung, Yan Chong, Andrew Bellis, Philip Clarke +1 more 2011-08-02
7983094 PVT compensated auto-calibration scheme for DDR3 Manoj B. Roge, Andrew Bellis, Philip Clarke, Joseph Huang, Yan Chong 2011-07-19
7928770 I/O block for high performance memory interfaces Andrew Bellis, Philip Clarke, Joseph Huang, Yan Chong, Manoj B. Roge 2011-04-19
7876630 Postamble timing for DDR memories Philip Clarke, Andrew Bellis, Yan Chong, Joseph Huang 2011-01-25
7706996 Write-side calibration for data interface Yan Chong, Chiakang Sung, Joseph Huang 2010-04-27
7593273 Read-leveling implementations for DDR3 applications on an FPGA Joseph Huang, Chiakang Sung, Yan Chong, Andrew Bellis, Philip Clarke +1 more 2009-09-22
7589556 Dynamic control of memory interface timing Johnson Tan, Andrew Bellis, Philip Clarke, Yan Chong, Joseph Huang +1 more 2009-09-15
7590008 PVT compensated auto-calibration scheme for DDR3 Manoj B. Roge, Andrew Bellis, Philip Clarke, Joseph Huang, Yan Chong 2009-09-15
7509223 Read-side calibration for data interface Yan Chong, Chiakang Sung, Joseph Huang 2009-03-24
7492185 Innovated technique to reduce memory interface write mode SSN in FPGA Joseph Huang, Chiakang Sung, Yan Chong 2009-02-17
7330051 Innovated technique to reduce memory interface write mode SSN in FPGA Joseph Huang, Chiakang Sung, Yan Chong 2008-02-12