| 8671303 |
Write-leveling implementation in programmable logic devices |
Yan Chong, Bonnie I. Wang, Chiakang Sung, Joseph Huang |
2014-03-11 |
$8,295,000 |
| 8122275 |
Write-leveling implementation in programmable logic devices |
Yan Chong, Bonnie I. Wang, Chiakang Sung, Joseph Huang |
2012-02-21 |
$11,276,000 |
| 7990783 |
Postamble timing for DDR memories |
Philip Clarke, Andrew Bellis, Yan Chong, Joseph Huang |
2011-08-02 |
$9,237,000 |
| 7990786 |
Read-leveling implementations for DDR3 applications on an FPGA |
Joseph Huang, Chiakang Sung, Yan Chong, Andrew Bellis, Philip Clarke +1 more |
2011-08-02 |
$9,237,000 |
| 7983094 |
PVT compensated auto-calibration scheme for DDR3 |
Manoj B. Roge, Andrew Bellis, Philip Clarke, Joseph Huang, Yan Chong |
2011-07-19 |
$8,014,000 |
| 7928770 |
I/O block for high performance memory interfaces |
Andrew Bellis, Philip Clarke, Joseph Huang, Yan Chong, Manoj B. Roge |
2011-04-19 |
$23,471,000 |
| 7876630 |
Postamble timing for DDR memories |
Philip Clarke, Andrew Bellis, Yan Chong, Joseph Huang |
2011-01-25 |
$13,497,000 |
| 7706996 |
Write-side calibration for data interface |
Yan Chong, Chiakang Sung, Joseph Huang |
2010-04-27 |
$8,832,000 |
| 7593273 |
Read-leveling implementations for DDR3 applications on an FPGA |
Joseph Huang, Chiakang Sung, Yan Chong, Andrew Bellis, Philip Clarke +1 more |
2009-09-22 |
$8,877,000 |
| 7589556 |
Dynamic control of memory interface timing |
Johnson Tan, Andrew Bellis, Philip Clarke, Yan Chong, Joseph Huang +1 more |
2009-09-15 |
$4,211,000 |
| 7590008 |
PVT compensated auto-calibration scheme for DDR3 |
Manoj B. Roge, Andrew Bellis, Philip Clarke, Joseph Huang, Yan Chong |
2009-09-15 |
$4,211,000 |
| 7509223 |
Read-side calibration for data interface |
Yan Chong, Chiakang Sung, Joseph Huang |
2009-03-24 |
$7,911,000 |
| 7492185 |
Innovated technique to reduce memory interface write mode SSN in FPGA |
Joseph Huang, Chiakang Sung, Yan Chong |
2009-02-17 |
$5,351,000 |
| 7330051 |
Innovated technique to reduce memory interface write mode SSN in FPGA |
Joseph Huang, Chiakang Sung, Yan Chong |
2008-02-12 |
$6,466,000 |
