Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7990786 | Read-leveling implementations for DDR3 applications on an FPGA | Michael H. M. Chu, Joseph Huang, Chiakang Sung, Yan Chong, Andrew Bellis +1 more | 2011-08-02 |
| 7983094 | PVT compensated auto-calibration scheme for DDR3 | Andrew Bellis, Philip Clarke, Joseph Huang, Michael H. M. Chu, Yan Chong | 2011-07-19 |
| 7928770 | I/O block for high performance memory interfaces | Andrew Bellis, Philip Clarke, Joseph Huang, Yan Chong, Michael H. M. Chu | 2011-04-19 |
| 7660167 | Memory device and method for fast cross row data access | Rajesh Manapat | 2010-02-09 |
| 7593273 | Read-leveling implementations for DDR3 applications on an FPGA | Michael H. M. Chu, Joseph Huang, Chiakang Sung, Yan Chong, Andrew Bellis +1 more | 2009-09-22 |
| 7590008 | PVT compensated auto-calibration scheme for DDR3 | Andrew Bellis, Philip Clarke, Joseph Huang, Michael H. M. Chu, Yan Chong | 2009-09-15 |
| 6791898 | Memory device providing asynchronous and synchronous data transfer | Rajesh Manapat, Kannan Srinivasagam | 2004-09-14 |
| 6721202 | Bit encoded ternary content addressable memory cell | Ajay Srikrishna | 2004-04-13 |
| 6480406 | Content addressable memory cell | Bo Jin | 2002-11-12 |
| 6384621 | Programmable transmission line impedance matching circuit | Gary A. Gibbs | 2002-05-07 |