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USPTO Patent Rankings Data through Dec 31, 2025
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Philip Clarke — 14 Patents

Intel: 14 patents #2,935 of 30,777Top 10%
Leatherhead, GB: #27 of 776 inventorsTop 4%
Overall (All Time): #332,869 of 4,157,543Top 9%
14 Patents All Time
Philip Clarke has been granted 14 US patents while listed as an inventor at Intel. The first was granted in 2009 and the most recent in October 2016. Philip Clarke ranks #332,869 of 4,157,543 US inventors in our database (top 8.0%). Patent records list Philip Clarke in Leatherhead, GB.

Issued Patents All Time

Showing 1–14 of 14 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
9477586 Power-aware memory controller circuitry Sam Hedinger 2016-10-25
8223584 Apparatus for memory interface configuration 2012-07-17 $17,885,000
7990786 Read-leveling implementations for DDR3 applications on an FPGA Michael H. M. Chu, Joseph Huang, Chiakang Sung, Yan Chong, Andrew Bellis +1 more 2011-08-02 $9,237,000
7990783 Postamble timing for DDR memories Andrew Bellis, Yan Chong, Joseph Huang, Michael H. M. Chu 2011-08-02 $9,237,000
7983094 PVT compensated auto-calibration scheme for DDR3 Manoj B. Roge, Andrew Bellis, Joseph Huang, Michael H. M. Chu, Yan Chong 2011-07-19 $8,014,000
7928770 I/O block for high performance memory interfaces Andrew Bellis, Joseph Huang, Yan Chong, Michael H. M. Chu, Manoj B. Roge 2011-04-19 $23,471,000
7898296 Distribution and synchronization of a divided clock signal Ning Xue, Joseph Huang, Yan Chong 2011-03-01 $14,298,000
7876630 Postamble timing for DDR memories Andrew Bellis, Yan Chong, Joseph Huang, Michael H. M. Chu 2011-01-25 $13,497,000
7791375 DQS re sync calibration 2010-09-07 $8,149,000
7688116 Read data path Philip S. Wise 2010-03-30 $8,741,000
7642812 Distribution and synchronization of a divided clock signal Ning Xue, Joseph Huang, Yan Chong 2010-01-05 $7,336,000
7593273 Read-leveling implementations for DDR3 applications on an FPGA Michael H. M. Chu, Joseph Huang, Chiakang Sung, Yan Chong, Andrew Bellis +1 more 2009-09-22 $8,877,000
7589556 Dynamic control of memory interface timing Johnson Tan, Andrew Bellis, Yan Chong, Joseph Huang, Michael H. M. Chu +1 more 2009-09-15 $4,211,000
7590008 PVT compensated auto-calibration scheme for DDR3 Manoj B. Roge, Andrew Bellis, Joseph Huang, Michael H. M. Chu, Yan Chong 2009-09-15 $4,211,000