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Power-aware memory controller circuitry |
Sam Hedinger |
2016-10-25 |
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Apparatus for memory interface configuration |
— |
2012-07-17 |
| 7990786 |
Read-leveling implementations for DDR3 applications on an FPGA |
Michael H. M. Chu, Joseph Huang, Chiakang Sung, Yan Chong, Andrew Bellis +1 more |
2011-08-02 |
| 7990783 |
Postamble timing for DDR memories |
Andrew Bellis, Yan Chong, Joseph Huang, Michael H. M. Chu |
2011-08-02 |
| 7983094 |
PVT compensated auto-calibration scheme for DDR3 |
Manoj B. Roge, Andrew Bellis, Joseph Huang, Michael H. M. Chu, Yan Chong |
2011-07-19 |
| 7928770 |
I/O block for high performance memory interfaces |
Andrew Bellis, Joseph Huang, Yan Chong, Michael H. M. Chu, Manoj B. Roge |
2011-04-19 |
| 7898296 |
Distribution and synchronization of a divided clock signal |
Ning Xue, Joseph Huang, Yan Chong |
2011-03-01 |
| 7876630 |
Postamble timing for DDR memories |
Andrew Bellis, Yan Chong, Joseph Huang, Michael H. M. Chu |
2011-01-25 |
| 7791375 |
DQS re sync calibration |
— |
2010-09-07 |
| 7688116 |
Read data path |
Philip S. Wise |
2010-03-30 |
| 7642812 |
Distribution and synchronization of a divided clock signal |
Ning Xue, Joseph Huang, Yan Chong |
2010-01-05 |
| 7593273 |
Read-leveling implementations for DDR3 applications on an FPGA |
Michael H. M. Chu, Joseph Huang, Chiakang Sung, Yan Chong, Andrew Bellis +1 more |
2009-09-22 |
| 7589556 |
Dynamic control of memory interface timing |
Johnson Tan, Andrew Bellis, Yan Chong, Joseph Huang, Michael H. M. Chu +1 more |
2009-09-15 |
| 7590008 |
PVT compensated auto-calibration scheme for DDR3 |
Manoj B. Roge, Andrew Bellis, Joseph Huang, Michael H. M. Chu, Yan Chong |
2009-09-15 |