Issued Patents All Time
Showing 25 most recent of 120 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9711189 | On-die input reference voltage with self-calibrating duty cycle correction | Chiakang Sung, Xiaobao Wang, Yan Chong, Joseph Huang, Khai Nguyen +1 more | 2017-07-18 |
| 9473145 | Programmable high-speed I/O interface | Chiakang Sung, Joseph Huang, Khai Nguyen, Philip Pan | 2016-10-18 |
| 9385718 | Input-output buffer circuit with a gate bias generator | Jun Liu, Yanzhong Xu, Jeffrey T. Watt | 2016-07-05 |
| 9330218 | Integrated circuits having input-output circuits with dedicated memory controller circuitry | Gordon Raymond Chiu, Sean Shau-Tu Lu, Warren Nordyke, Weizhong Xu | 2016-05-03 |
| 9166589 | Multiple data rate interface architecture | Philip Pan, Chiakang Sung, Joseph Huang, Yan Chong | 2015-10-20 |
| 9106230 | Input-output circuitry for integrated circuits | Warren Nordyke, Weiqi Ding, Yan Chong | 2015-08-11 |
| 9099999 | Adjustable drive strength input-output buffer circuitry | Chiakang Sung, Joseph Huang, Khai Nguyen, Tony Ngai, Zhe Li +1 more | 2015-08-04 |
| 9065399 | Programmable high-speed voltage-mode differential driver | Weiqi Ding, Tim Tri Hoang, Richard Hernandez, Haidang Lin | 2015-06-23 |
| 8854078 | Dynamic termination-impedance control for bidirectional I/O pins | Xiaobao Wang, Chiakang Sung, Khai Nguyen | 2014-10-07 |
| 8829948 | Programmable high-speed I/O interface | Chiakang Sung, Joseph Huang, Khai Nguyen, Philip Pan | 2014-09-09 |
| 8671303 | Write-leveling implementation in programmable logic devices | Yan Chong, Chiakang Sung, Joseph Huang, Michael H. M. Chu | 2014-03-11 |
| 8610462 | Input-output circuit and method of improving input-output signals | Xiaobao Wang, Chiakang Sung, Khai Nguyen | 2013-12-17 |
| 8575957 | Multiple data rate interface architecture | Philip Pan, Chiakang Sung, Joseph Huang, Yan Chong | 2013-11-05 |
| 8531205 | Programmable output buffer | Chiakang Sung, Xiaobao Wang, Khai Nguyen, Joseph Huang | 2013-09-10 |
| 8487665 | Programmable high-speed interface | Chiakang Sung, Joseph Huang, Khai Nguyen, Philip Pan | 2013-07-16 |
| 8384460 | Techniques for phase adjustment | Chiakang Sung, John Henry Bui, Khai Nguyen, Xiaobao Wang | 2013-02-26 |
| 8149038 | Techniques for phase adjustment | Chiakang Sung, John Henry Bui, Khai Nguyen, Xiaobao Wang | 2012-04-03 |
| 8122275 | Write-leveling implementation in programmable logic devices | Yan Chong, Chiakang Sung, Joseph Huang, Michael H. M. Chu | 2012-02-21 |
| 8098082 | Multiple data rate interface architecture | Philip Pan, Chiakang Sung, Joseph Huang, Yan Chong | 2012-01-17 |
| 8022723 | Dynamic termination-impedance control for bidirectional I/O pins | Xiaobao Wang, Chiakang Sung, Khai Nguyen | 2011-09-20 |
| 7973553 | Techniques for on-chip termination | Xiaobao Wang, Chiakang Sung, Khai Nguyen, John Henry Bui | 2011-07-05 |
| 7859304 | Multiple data rate interface architecture | Philip Pan, Chiakang Sung, Joseph Huang, Yan Chong | 2010-12-28 |
| 7725755 | Self-compensating delay chain for multiple-date-rate interfaces | Yan Chong, Chiakang Sung, Joseph Huang, Xiaobao Wang, Philip Pan +1 more | 2010-05-25 |
| 7710149 | Input buffer for multiple differential I/O standards | Jonathan Chung, In Whan Kim, Philip Pan, Chiakang Sung, Xiabao Wang +5 more | 2010-05-04 |
| 7590879 | Clock edge de-skew | Henry Kim, Chiakang Sung, Joseph Huang | 2009-09-15 |