Issued Patents All Time
Showing 25 most recent of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11791821 | Fast FPGA interconnect stitching for wire highways | Marcel Gort, Brett Grady, Kara Poon | 2023-10-17 |
| 10797702 | Apparatus for flexible electronic interfaces and associated methods | — | 2020-10-06 |
| 10476505 | Apparatus for flexible electronic interfaces and associated methods | — | 2019-11-12 |
| 10063235 | Apparatus for flexible electronic interfaces and associated methods | — | 2018-08-28 |
| 9966362 | Integrated circuit package with inter-die thermal spreader layers | Arifur Rahman | 2018-05-08 |
| 9825633 | Heterogeneous segmented and direct routing architecture for field programmable gate array | — | 2017-11-21 |
| 9647668 | Apparatus for flexible electronic interfaces and associated methods | — | 2017-05-09 |
| 9525419 | Heterogeneous segmented and direct routing architecture for field programmable gate array | — | 2016-12-20 |
| 9501407 | First-in-first-out memory with dual memory banks | Ray Ruey-Hsien Hu, Andy L. Lee, David Lewis, Haiming Yu, Hao-Yuan Howard Chou | 2016-11-22 |
| 9490811 | Fine grain programmable gate architecture with hybrid logic/routing element and direct-drive routing | — | 2016-11-08 |
| 9099999 | Adjustable drive strength input-output buffer circuitry | Bonnie I. Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Zhe Li +1 more | 2015-08-04 |
| 9030253 | Integrated circuit package with distributed clock network | — | 2015-05-12 |
| 8941233 | Integrated circuit package with inter-die thermal spreader layers | Arifur Rahman | 2015-01-27 |
| 8901961 | Placement, rebuffering and routing structure for PLD interface | Arifur Rahman, Curt Wortman | 2014-12-02 |
| 8760328 | Interface circuitry for an integrated circuit system | Wei Yee Koay, Chin-Ghee Ch'ng, Ket Chiew Sia, Sean Woei Voon | 2014-06-24 |
| 8739099 | Method and apparatus for determining clock uncertainties | Victor Maruri, Boon Jin Ang, Henry Y. Lui, Surinder Singh, Thow Pang Chong | 2014-05-27 |
| 8645450 | Multiplier-accumulator circuitry and methods | Kok Heng Choe, Henry Y. Lui | 2014-02-04 |
| 7839167 | Interconnection and input/output resources for programmable logic integrated circuit devices | Bruce B. Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Michael D. Hutton +6 more | 2010-11-23 |
| RE41325 | Dual port random-access-memory circuitry | Haiming Yu, Kok Heng Choe | 2010-05-11 |
| 7492188 | Interconnection and input/output resources for programmable logic integrated circuit devices | Bruce B. Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Michael D. Hutton +6 more | 2009-02-17 |
| 7471588 | Dual port random-access-memory circuitry | Haiming Yu, Kok Heng Choe | 2008-12-30 |
| 7417918 | Method and apparatus for configuring the operating speed of a programmable logic device through a self-timed reference circuit | Eunice Y. D. Hao, Jennifer Wong, Alvin Y. Ching | 2008-08-26 |
| 7317332 | Interconnection and input/output resources for programmable logic integrated circuit devices | Bruce B. Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Victor Maruri +1 more | 2008-01-08 |
| 7262635 | Interconnection resources for programmable logic integrated circuit devices | James Schleicher, Jim Park, Sergey Shumarayev, Bruce B. Pedersen, Wei-Jen Huang +2 more | 2007-08-28 |
| 7254677 | First-in, first-out memory system with reduced cycle latency | Wayson J. Lowe, Eunice Y. D. Hao, Peter H. Alfke | 2007-08-07 |