Issued Patents All Time
Showing 25 most recent of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8352526 | Direct digital synthesis with reduced jitter | — | 2013-01-08 |
| 8265902 | Circuit for measuring a time interval using a high-speed serial receiver | Noel J. Brady, Lionel Barker | 2012-09-11 |
| 7839181 | Glitch-suppressor circuits and methods | — | 2010-11-23 |
| 7759801 | Tapered signal lines | Austin H. Lesea | 2010-07-20 |
| 7755381 | Reducing noise on a supply voltage in an integrated circuit | Mark A. Alexander | 2010-07-13 |
| 7667500 | Glitch-suppressor circuits and methods | — | 2010-02-23 |
| 7574635 | Circuit for and method of testing a memory device | — | 2009-08-11 |
| 7535789 | Circuits and methods of concatenating FIFOs | Thomas E. Fischaber, James M. Simkins | 2009-05-19 |
| 7291923 | Tapered signal lines | Austin H. Lesea | 2007-11-06 |
| 7268594 | Direct digital synthesis with low jitter | — | 2007-09-11 |
| 7254677 | First-in, first-out memory system with reduced cycle latency | Wayson J. Lowe, Eunice Y. D. Hao, Tony Ngai | 2007-08-07 |
| 7227387 | Measuring pulse edge delay value relative to a clock using multiple delay devices to address a memory to access the delay value | — | 2007-06-05 |
| 7161849 | First-in, first-out buffer system in an integrated circuit | Wayson J. Lowe, Eunice Y. D. Hao, Tony Ngai | 2007-01-09 |
| 7057413 | Large crossbar switch implemented in FPGA | Steven P. Young, Trevor J. Bauer, Colm P. Fewer | 2006-06-06 |
| 7020862 | Circuits and methods for analyzing timing characteristics of sequential logic elements | Himanshu Verma | 2006-03-28 |
| 6956776 | Almost full, almost empty memory system | Wayson J. Lowe, Eunice Y. D. Hao, Tony Ngai | 2005-10-18 |
| 6937172 | Method and system for gray-coding counting | Wayson J. Lowe, Eunice Y. D. Hao, Tony Ngai | 2005-08-30 |
| 6934198 | First-in, first-out buffer system in an integrated circuit | Wayson J. Lowe, Eunice Y. D. Hao, Tony Ngai | 2005-08-23 |
| 6810514 | Controller arrangement for partial reconfiguration of a programmable logic device | Scott P. McMillan, Brandon J. Blodget, Delon Levi | 2004-10-26 |
| 6759869 | Large crossbar switch implemented in FPGA | Steven P. Young, Trevor J. Bauer, Colm P. Fewer | 2004-07-06 |
| 6734703 | Circuits and methods for analyzing timing characteristics of sequential logic elements | Himanshu Verma | 2004-05-11 |
| 6441641 | Programmable logic device with partial battery backup | Raymond C. Pang, Venu M. Kondapalli, Jane W. Sowards, Scott O. Frake, Jennifer Wong +2 more | 2002-08-27 |
| 6434642 | FIFO memory system and method with improved determination of full and empty conditions and amount of data stored | Nicolas John Camilleri, Christopher D. Ebeling | 2002-08-13 |
| 6407612 | Method and system for suppressing input signal irregularities | — | 2002-06-18 |
| 6389490 | FIFO memory system and method with improved generation of empty and full control signals in one clock cycle using almost empty and almost full signals | Nicolas John Camilleri | 2002-05-14 |