| 7669163 |
Partial configuration of a programmable gate array using a bus macro and coupling the third design |
Edward S. McGettigan |
2010-02-23 |
| 7024651 |
Partial reconfiguration of a programmable gate array using a bus macro |
Edward S. McGettigan |
2006-04-04 |
| 6732347 |
Clock template for configuring a programmable gate array |
Edward S. McGettigan, Kenneth J. Stickney, Jr., Jeffrey V. Lindholm, Kevin Bixler, Raymond Kong |
2004-05-04 |
| 6462579 |
Partial reconfiguration of a programmable gate array using a bus macro |
Edward S. McGettigan |
2002-10-08 |
| 6434642 |
FIFO memory system and method with improved determination of full and empty conditions and amount of data stored |
Peter H. Alfke, Christopher D. Ebeling |
2002-08-13 |
| 6405269 |
FIFO memory including a comparator circuit for determining full/empty conditions using mode control and carry chain multiplexers |
Christopher D. Ebeling |
2002-06-11 |
| 6401148 |
FIFO memory system and method with improved determination of amount of data stored using a binary read address synchronized to a write clock |
— |
2002-06-04 |
| 6389490 |
FIFO memory system and method with improved generation of empty and full control signals in one clock cycle using almost empty and almost full signals |
Peter H. Alfke |
2002-05-14 |
| 6107827 |
FPGA CLE with two independent carry chains |
Steven P. Young, Bernard J. New, Trevor J. Bauer, Shekhar Bapat, Kamal Chaudhary +1 more |
2000-08-22 |
| 5963050 |
Configurable logic element with fast feedback paths |
Steven P. Young, Bernard J. New, Trevor J. Bauer, Shekhar Bapat, Kamal Chaudhary +1 more |
1999-10-05 |