Issued Patents All Time
Showing 25 most recent of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8593176 | One phase logic | Raymond Nijssen, Rajit Manohar, Christopher LaFrieda, Clinton W. Kelly, Virantha Ekanayake | 2013-11-26 |
| 8191019 | Non-predicated to predicated conversion of asynchronous representations | Rajit Manohar, Ilya K. Ganusov, Virantha Ekanayake, Clinton W. Kelly | 2012-05-29 |
| 8146041 | Latch based optimization during implementation of circuit designs for programmable logic devices | Sankaranarayanan Srinivasan, Sridhar Krishnamurthy, Brian D. Philofsky, Anirban Rahut | 2012-03-27 |
| 8106683 | One phase logic | Raymond Nijssen, Rajit Manohar, Christopher LaFrieda, Clinton W. Kelly, Virantha Ekanayake | 2012-01-31 |
| 8010923 | Latch based optimization during implementation of circuit designs for programmable logic devices | Sankaranarayanan Srinivasan, Sridhar Krishnamurthy, Brian D. Philofsky, Anirban Rahut | 2011-08-30 |
| 7932746 | One phase logic | Raymond Nijssen, Rajit Manohar, Christopher LaFrieda, Clinton W. Kelly, Virantha Ekanayake | 2011-04-26 |
| 7853914 | Fanout-optimization during physical synthesis for placed circuit designs | Sankaranarayanan Srinivasan, Amit Singh, Benoit Payette | 2010-12-14 |
| 7590960 | Placing partitioned circuit designs within iterative implementation flows | Raymond Kong, Navaratnasothie Selvakkumaran | 2009-09-15 |
| 7536661 | Incremental placement during physical synthesis | Amit Singh | 2009-05-19 |
| 7428718 | Enhanced incremental placement during physical synthesis | Amit Singh | 2008-09-23 |
| 7146590 | Congestion estimation for programmable logic devices | — | 2006-12-05 |
| 7111214 | Circuits and methods for testing programmable logic devices using lookup tables and carry chains | Sridhar Krishnamurthy | 2006-09-19 |
| 7075333 | Programmable circuit optionally configurable as a lookup table or a wide multiplexer | Philip D. Costello, Venu M. Kondapalli | 2006-07-11 |
| 7072815 | Relocation of components for post-placement optimization | Krishnan Anandh, Sudip K. Nag, Guenter Stenz | 2006-07-04 |
| 7058915 | Pin reordering during placement of circuit designs | Amit Singh | 2006-06-06 |
| 6484298 | Method and apparatus for automatic timing-driven implementation of a circuit design | Sudip K. Nag, Jason H. Anderson, Madabhushi V. R. Chari, Sandor S. Kalman | 2002-11-19 |
| 6448808 | Interconnect structure for a programmable logic device | Steven P. Young, Trevor J. Bauer | 2002-09-10 |
| 6415425 | Method for analytical placement of cells using density surface representations | Sudip K. Nag | 2002-07-02 |
| 6362648 | Multiplexer for implementing logic functions in a programmable logic device | Bernard J. New, Steven P. Young, Shekhar Bapat, Trevor J. Bauer, Roman Iwanczuk | 2002-03-26 |
| 6336208 | Delay optimized mapping for programmable gate arrays with multiple sized lookup tables | Sundararajarao Mohan | 2002-01-01 |
| 6292022 | Interconnect structure for a programmable logic device | Steven P. Young, Trevor J. Bauer | 2001-09-18 |
| 6204690 | FPGA architecture with offset interconnect lines | Steven P. Young, Trevor J. Bauer | 2001-03-20 |
| 6201410 | Wide logic gate implemented in an FPGA configurable logic element | Bernard J. New, Steven P. Young, Shekhar Bapat, Trevor J. Bauer, Roman Iwanczuk | 2001-03-13 |
| 6124731 | Configurable logic element with ability to evaluate wide logic functions | Steven P. Young, Shekhar Bapat, Trevor J. Bauer, Roman Iwanczuk | 2000-09-26 |
| 6107827 | FPGA CLE with two independent carry chains | Steven P. Young, Bernard J. New, Nicolas John Camilleri, Trevor J. Bauer, Shekhar Bapat +1 more | 2000-08-22 |