Issued Patents All Time
Showing 25 most recent of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9405871 | Determination of path delays in circuit designs | Nagaraj Savithri, Vinod Kumar Nakkala, Atul Srinivasan | 2016-08-02 |
| 8448122 | Implementing sub-circuits with predictable behavior within a circuit design | Vishal Suthar, Hasan Arslan, Sridhar Krishnamurthy, Sanjeev Kwatra, Srinivasan Dasasathyan +1 more | 2013-05-21 |
| 7728623 | Programmable logic cells with local connections | Hare K. Verma, Ravi Sunkavalli, Conrad Kong, Bo Hu, Chandra Mulpuri +1 more | 2010-06-01 |
| 7725868 | Method and apparatus for facilitating signal routing within a programmable logic device | Vinay Verma, Anirban Rahut, Jason H. Anderson, Rajeev Jayaraman | 2010-05-25 |
| 7605605 | Programmable logic cells with local connections | Hare K. Verma, Ravi Sunkavalli, Conrad Kong, Bo Hu, Chandra Mulpuri +1 more | 2009-10-20 |
| 7428722 | Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes | Ravi Sunkavalli, Hare K. Verma, Elliott Delaye | 2008-09-23 |
| 7398496 | Unified placer infrastructure | James L. Saunders, Krishnan Anandh, Guenther Stenz, Jason H. Anderson | 2008-07-08 |
| 7358761 | Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes | Ravi Sunkavalli, Hare K. Verma, Elliott Delaye | 2008-04-15 |
| 7306977 | Method and apparatus for facilitating signal routing within a programmable logic device | Vinay Verma, Anirban Rahut, Jason H. Anderson, Rajeev Jayaraman | 2007-12-11 |
| 7240315 | Automated local clock placement for FPGA designs | Qiang Wang, Srinivasan Dasasathyan, James L. Saunders, Pavanish Nirula | 2007-07-03 |
| 7143378 | Method and apparatus for timing characterization of integrated circuit designs | — | 2006-11-28 |
| 7143380 | Method for application of network flow techniques under constraints | Jason H. Anderson, Guenter Stenz, Srinivasan Dasasathyan | 2006-11-28 |
| 7076758 | Using router feedback for placement improvements for logic design | Sankaranarayanan Srinivasan, Anirban Rahut, Krishnan Anandh | 2006-07-11 |
| 7072815 | Relocation of components for post-placement optimization | Kamal Chaudhary, Krishnan Anandh, Guenter Stenz | 2006-07-04 |
| 7051312 | Upper-bound calculation for placed circuit design performance | Anirban Rahut | 2006-05-23 |
| 6983439 | Unified placer infrastructure | James L. Saunders, Krishnan Anandh, Guenter Stenz, Jason H. Anderson | 2006-01-03 |
| 6877040 | Method and apparatus for testing routability | Gi-Joon Nam, Sandor S. Kalman, Jason H. Anderson, Rajeev Jayaraman, Jennifer Zhuang | 2005-04-05 |
| 6857115 | Placement of objects with partial shape restriction | Srinivasan Dasasathyan, Guenter Stenz, Jason H. Anderson | 2005-02-15 |
| 6789244 | Placement of clock objects under constraints | Srinivasan Dasasathyan, Guenter Stenz | 2004-09-07 |
| 6766504 | Interconnect routing using logic levels | Anirban Rahut | 2004-07-20 |
| 6732349 | Method and apparatus for improving PIP coverage in programmable logic devices | Richard Yachyang Sun, Sandor S. Kalman | 2004-05-04 |
| 6711600 | System and method for RAM-partitioning to exploit parallelism of RADIX-2 elements in FPGAs | Hare K. Verma | 2004-03-23 |
| 6625795 | Method and apparatus for placement of input-output design objects into a programmable gate array | Jason H. Anderson, James L. Saunders, Madabhushi V. R. Chari, Rajeev Jayaraman | 2003-09-23 |
| 6507860 | System and method for RAM-partitioning to exploit parallelism of RADIX-2 elements in FPGAs | Hare K. Verma | 2003-01-14 |
| 6484298 | Method and apparatus for automatic timing-driven implementation of a circuit design | Kamal Chaudhary, Jason H. Anderson, Madabhushi V. R. Chari, Sandor S. Kalman | 2002-11-19 |