Rajeev Jayaraman — 8 Patents at AMD

Rajeev Jayaraman has been granted 8 US patents while listed as an inventor at AMD. The first was granted in 2001 and the most recent in July 2011. Rajeev Jayaraman ranks #600,572 of 4,157,543 US inventors in our database (top 14.4%). Patent records list Rajeev Jayaraman in San Jose, CA, US.

Issued Patents All Time

Showing 1–8 of 8 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
7979816	Method and apparatus for implementing a circuit design for an integrated circuit	Arne S. Barras	2011-07-12	$5,959,000
7725868	Method and apparatus for facilitating signal routing within a programmable logic device	Vinay Verma, Anirban Rahut, Sudip K. Nag, Jason H. Anderson	2010-05-25	$2,818,000
7380219	Method and apparatus for implementing a circuit design for an integrated circuit	Arne S. Barras	2008-05-27	$3,924,000
7306977	Method and apparatus for facilitating signal routing within a programmable logic device	Vinay Verma, Anirban Rahut, Sudip K. Nag, Jason H. Anderson	2007-12-11	$5,722,000
7185299	Methods of estimating routing delays during the placement process in programmable logic devices	—	2007-02-27	$8,509,000
6877040	Method and apparatus for testing routability	Gi-Joon Nam, Sandor S. Kalman, Jason H. Anderson, Sudip K. Nag, Jennifer Zhuang	2005-04-05	$9,412,000
6625795	Method and apparatus for placement of input-output design objects into a programmable gate array	Jason H. Anderson, James L. Saunders, Madabhushi V. R. Chari, Sudip K. Nag	2003-09-23	$17,402,000
6289496	Placement of input-output design objects into a programmable gate array supporting multiple voltage standards	Jason H. Anderson, James L. Saunders, Madabhushi V. R. Chari, Sudip K. Nag	2001-09-11

Rajeev Jayaraman — 8 Patents

Issued Patents All Time

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