Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7979816 | Method and apparatus for implementing a circuit design for an integrated circuit | Arne S. Barras | 2011-07-12 |
| 7725868 | Method and apparatus for facilitating signal routing within a programmable logic device | Vinay Verma, Anirban Rahut, Sudip K. Nag, Jason H. Anderson | 2010-05-25 |
| 7380219 | Method and apparatus for implementing a circuit design for an integrated circuit | Arne S. Barras | 2008-05-27 |
| 7306977 | Method and apparatus for facilitating signal routing within a programmable logic device | Vinay Verma, Anirban Rahut, Sudip K. Nag, Jason H. Anderson | 2007-12-11 |
| 7185299 | Methods of estimating routing delays during the placement process in programmable logic devices | — | 2007-02-27 |
| 6877040 | Method and apparatus for testing routability | Gi-Joon Nam, Sandor S. Kalman, Jason H. Anderson, Sudip K. Nag, Jennifer Zhuang | 2005-04-05 |
| 6625795 | Method and apparatus for placement of input-output design objects into a programmable gate array | Jason H. Anderson, James L. Saunders, Madabhushi V. R. Chari, Sudip K. Nag | 2003-09-23 |
| 6289496 | Placement of input-output design objects into a programmable gate array supporting multiple voltage standards | Jason H. Anderson, James L. Saunders, Madabhushi V. R. Chari, Sudip K. Nag | 2001-09-11 |