Anirban Rahut — 24 Patents at AMD

Anirban Rahut has been granted 24 US patents while listed as an inventor at AMD. The first was granted in 2004 and the most recent in April 2025. Anirban Rahut ranks #168,038 of 4,157,543 US inventors in our database (top 4.0%). Patent records list Anirban Rahut in Santa Clara, CA, US.

Patents per Year

Issued Patents All Time

Showing 1–24 of 24 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
12282497	Search result replication management in a search head cluster	Sundar Rengarajan Vasan	2025-04-22
11704341	Search result replication management in a search head cluster	Sundar Rengarajan Vasan	2023-07-18	$26,279,000
10698777	High availability scheduler for scheduling map-reduce searches based on a leader state	—	2020-06-30	$48,252,000
10133806	Search result replication in a search head cluster	Sundar Rengarajan Vasan	2018-11-20	$62,655,000
9983954	High availability scheduler for scheduling searches of time stamped events	—	2018-05-29	$25,097,000
9256501	High availability scheduler for scheduling map-reduce searches	—	2016-02-09	$37,535,000
9047246	High availability scheduler	—	2015-06-02	$42,519,000
8146041	Latch based optimization during implementation of circuit designs for programmable logic devices	Sankaranarayanan Srinivasan, Sridhar Krishnamurthy, Brian D. Philofsky, Kamal Chaudhary	2012-03-27	$2,711,000
8015535	Run-time efficient methods for routing large multi-fanout nets	Raymond Kong	2011-09-06	$6,865,000
8010923	Latch based optimization during implementation of circuit designs for programmable logic devices	Sankaranarayanan Srinivasan, Sridhar Krishnamurthy, Brian D. Philofsky, Kamal Chaudhary	2011-08-30	$13,546,000
7904860	Method and apparatus for selecting programmable interconnects to reduce clock skew	—	2011-03-08	$7,712,000
7797665	Patterns for routing nets in a programmable logic device	Hui Xu, Vinay Verma, Jason H. Anderson, Sandor S. Kalman	2010-09-14	$4,182,000
7735039	Methods of estimating net delays in tile-based PLD architectures	Srinivasan Dasasathyan, Hasan Arslan, Meng Lou	2010-06-08	$6,763,000
7725868	Method and apparatus for facilitating signal routing within a programmable logic device	Vinay Verma, Sudip K. Nag, Jason H. Anderson, Rajeev Jayaraman	2010-05-25	$2,818,000
7620923	Run-time efficient methods for routing large multi-fanout nets	Raymond Kong	2009-11-17	$2,669,000
7430728	Method and apparatus for selecting programmable interconnects to reduce clock skew	—	2008-09-30	$4,572,000
7424697	Assigning inputs of look-up tables to improve a design implementation in a programmable logic device	Hasan Arslan	2008-09-09	$8,560,000
7389485	Methods of routing low-power designs in programmable logic devices having heterogeneous routing architectures	Satyaki Das, Arifur Rahman	2008-06-17	$12,722,000
7376926	Run-time efficient methods for routing large multi-fanout nets	Raymond Kong	2008-05-20	$3,880,000
7306977	Method and apparatus for facilitating signal routing within a programmable logic device	Vinay Verma, Sudip K. Nag, Jason H. Anderson, Rajeev Jayaraman	2007-12-11	$5,722,000
7076758	Using router feedback for placement improvements for logic design	Sankaranarayanan Srinivasan, Krishnan Anandh, Sudip K. Nag	2006-07-11	$9,065,000
7051312	Upper-bound calculation for placed circuit design performance	Sudip K. Nag	2006-05-23	$20,425,000
6952813	Method and apparatus for selecting programmable interconnects to reduce clock skew	—	2005-10-04	$27,755,000
6766504	Interconnect routing using logic levels	Sudip K. Nag	2004-07-20	$41,367,000

Anirban Rahut — 24 Patents

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