Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11853662 | Machine-learning enhanced compiler | Senthilkumar Thoravi Rajavel, Vinod Kumar Nakkala, Avinash Anantharamu, Pierre Clement, Saibal Ghosh +2 more | 2023-12-26 |
| 11366948 | Machine-learning enhanced compiler | Senthilkumar Thoravi Rajavel, Vinod Kumar Nakkala, Avinash Anantharamu, Pierre Clement, Saibal Ghosh +2 more | 2022-06-21 |
| 8146041 | Latch based optimization during implementation of circuit designs for programmable logic devices | Sridhar Krishnamurthy, Brian D. Philofsky, Kamal Chaudhary, Anirban Rahut | 2012-03-27 |
| 8141010 | Method and arrangement providing for implementation granularity using implementation sets | Raymond Kong, Daniel J. Downs, John J. Laurence, Richard Yachyang Sun | 2012-03-20 |
| 8136073 | Circuit design fitting | Damon McCormick | 2012-03-13 |
| 8024696 | Clock speed for a digital circuit | Dinesh D. Gaitonde | 2011-09-20 |
| 8010923 | Latch based optimization during implementation of circuit designs for programmable logic devices | Sridhar Krishnamurthy, Brian D. Philofsky, Kamal Chaudhary, Anirban Rahut | 2011-08-30 |
| 7984415 | Merging of equivalent logic blocks in a circuit design | — | 2011-07-19 |
| 7979831 | Placement driven control set resynthesis | — | 2011-07-12 |
| 7853914 | Fanout-optimization during physical synthesis for placed circuit designs | Kamal Chaudhary, Amit Singh, Benoit Payette | 2010-12-14 |
| 7657855 | Efficient timing graph update for dynamic netlist changes | Walter A. Manaker, Jr., Nicholas A. Mezei, David Ewing | 2010-02-02 |
| 7636876 | Cost-based performance driven legalization technique for placement in logic designs | Srinivasan Dasasathyan | 2009-12-22 |
| 7392498 | Method and apparatus for implementing a pre-implemented circuit design for a programmable logic device | W. Story Leavesley, III, George L. McHugh, Douglas P. Wieland, Sandor S. Kalman | 2008-06-24 |
| 7360177 | Method and arrangement providing for implementation granularity using implementation sets | Raymond Kong, Daniel J. Downs, John J. Laurence, Richard Yachyang Sun | 2008-04-15 |
| 7181704 | Method and system for designing integrated circuits using implementation directives | Daniel J. Downs, Raymond Kong, John J. Laurence, Richard Yachyang Sun | 2007-02-20 |
| 7152217 | Alleviating timing based congestion within circuit designs | — | 2006-12-19 |
| 7076758 | Using router feedback for placement improvements for logic design | Anirban Rahut, Krishnan Anandh, Sudip K. Nag | 2006-07-11 |