Issued Patents All Time
Showing 25 most recent of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10366201 | Timing closure of circuit designs for integrated circuits | Aaron Ng, Grigor S. Gasparyan | 2019-07-30 |
| 10068048 | Generating clock trees for a circuit design | Mehrdad Eslami Dehkordi, Marvin Tom, Frank Mueller | 2018-09-04 |
| 10042971 | Placement and routing of clock signals for a circuit design | Mehrdad Eslami Dehkordi, Raoul Badaoui, Marvin Tom | 2018-08-07 |
| 9330220 | Clock region partitioning and clock routing | Mehrdad Eslami Dehkordi, Marvin Tom, Abhishek Joshi | 2016-05-03 |
| 9298868 | Hierarchical pushdown of cells and nets to any logical depth | Vikas Agrawal, Shrivathsa BHARGAVRAVICHANDRAN, Binh Pham, Jay Chen, Umang Shah +1 more | 2016-03-29 |
| 9042431 | Wide band deterministic interface | Venkat Yadavalli, Gerardo Orlando, David R. King, Ken Clauss, Mark Krumpoch +1 more | 2015-05-26 |
| 8448122 | Implementing sub-circuits with predictable behavior within a circuit design | Vishal Suthar, Hasan Arslan, Sanjeev Kwatra, Srinivasan Dasasathyan, Rajat Aggarwal +1 more | 2013-05-21 |
| 8146041 | Latch based optimization during implementation of circuit designs for programmable logic devices | Sankaranarayanan Srinivasan, Brian D. Philofsky, Kamal Chaudhary, Anirban Rahut | 2012-03-27 |
| 8010923 | Latch based optimization during implementation of circuit designs for programmable logic devices | Sankaranarayanan Srinivasan, Brian D. Philofsky, Kamal Chaudhary, Anirban Rahut | 2011-08-30 |
| 8005886 | Systems and methods for generating network messages | Paul G. Jacobsen, Scott Guillaudeu, David R. Freeman | 2011-08-23 |
| 7926016 | Timing driven logic block configuration | Priya Sundararajan | 2011-04-12 |
| 7784006 | Method and apparatus for directed physical implementation of a circuit design for an integrated circuit | Arnaud Duthou | 2010-08-24 |
| 7610573 | Implementation of alternate solutions in technology mapping and placement | Vi Chi Chan, Tetse Jang, Kevin Kwong-Tai Chung | 2009-10-27 |
| 7478356 | Timing driven logic block configuration | Priya Sundararajan | 2009-01-13 |
| 7249335 | Methods of routing programmable logic devices to minimize programming time | Jay T. Young, Jeffrey V. Lindholm | 2007-07-24 |
| 7143384 | Methods of routing programmable logic devices to minimize programming time | Jay T. Young, Jeffrey V. Lindholm | 2006-11-28 |
| 7111214 | Circuits and methods for testing programmable logic devices using lookup tables and carry chains | Kamal Chaudhary | 2006-09-19 |
| 7058919 | Methods of generating test designs for testing specific routing resources in programmable logic devices | Jay T. Young, Jeffrey V. Lindholm, Ian L. McEwen | 2006-06-06 |
| 6975990 | Sequential-data synchronization at real-time on an analog and a digital medium | Selvaraj Murugaiyan | 2005-12-13 |
| 6944809 | Methods of resource optimization in programmable logic devices to reduce test time | Andrew W. Lai, Randy J. Simmons, Teymour M. Mansour, Vincent L. Tong, Jeffrey V. Lindholm +2 more | 2005-09-13 |
| 6910002 | Method and apparatus for specifying addressability and bus connections in a logic design | Bart Reynolds, Cheng-I Chuang, Chukwuweta Chukwudebe, Damon McCormick, Tom Shui +1 more | 2005-06-21 |
| 6754760 | Programmable interface for a configurable system bus | Wilson K. Yee, Brian Fox, Bart Reynolds, Steven Winegarden | 2004-06-22 |
| 6661812 | Bidirectional bus for use as an interconnect routing resource | Bart Reynolds | 2003-12-09 |
| 6658547 | Method and apparatus for specifying address offsets and alignment in logic design | Bart Reynolds, Damon McCormick, Kai Zhu | 2003-12-02 |
| 6574655 | Associative management of multimedia assets and associated resources using multi-domain agent-based communication between heterogeneous peers | Scott Allan Libert, Robert J. Woolridge, Baochun Jin, Alex C. Tran, P. Murugavel +3 more | 2003-06-03 |